lowing equation:

(the T/H switch resistances).

To improve the input-signal bandwidth under AC

conditions, drive AIN with a wideband buffer

(> 4MHz) that can drive the ADC’s input capacitance

and settle quickly (see the

Input Buffer section).

An RC filter at AIN reduces the input track-and-hold

Analog Input Bandwidth

The MAX1069 features input-tracking circuitry with a

4MHz small-signal bandwidth. The 4MHz input band-

width makes it possible to digitize high-speed transient

events and measure periodic signals with bandwidths

exceeding the ADC’s sampling rate by using under-

sampling techniques. Use anti-alias filtering to avoid

high-frequency signals being aliased into the frequency

band of interest.

Analog Input Range and Protection

Internal ESD (electrostatic discharge) protection diodes

AGNDS/AGND (Figure 6). These diodes allow the ana-

0.3V) without causing damage to the device. For accu-

rate conversions, the inputs must not go more than

50mV beyond their rails.

If the analog inputs exceed 300mV beyond their

rails, limit the current to 2mA.

Internal Clock

The MAX1069 contains an internal 4MHz oscillator that

drives the SAR conversion clock. During conversion, SCL

is held low (clock stretching). An internal register stores

data when the conversion is in progress. When the

MAX1069 releases SCL, the master reads the conversion

results at any clock rate up to 1.7MHz (Figure 11).

Digital Interface

interface consisting of a bidirectional serial data line

(SDA) and a serial clock line (SCL). SDA and SCL facili-

tate bidirectional communication between the

MAX1069 and the master at rates up to 1.7MHz. The

master (typically a microcontroller) initiates data trans-

fer on the bus and generates SCL.

SDA and SCL require pullup resistors (500

Ω or greater,

Figure 4). Optional resistors (24

Ω) in series with SDA

and SCL protect the device inputs from high-voltage

spikes on the bus lines. Series resistors also minimize

crosstalk and undershoot of the bus signals.

Bit Transfer

One data bit is transferred during each SCL clock

cycle. Nine clock cycles are required to transfer the

data into or out of the MAX1069. The data on SDA must

remain stable during the high period of the SCL clock

pulse as changes in SDA while SCL is high are control

signals (see the

START and STOP Conditions section).

Both SDA and SCL idle high.

START and STOP Conditions

The master initiates a transmission with a START condi-

tion (S), a high-to-low transition on SDA with SCL high.

The master terminates a transmission with a STOP con-

dition (P), a low-to-high transition on SDA while SCL is

high (Figure 7). The STOP condition frees the bus and

places all devices in F/S mode (see the

Bus Timing

section). Use a repeated START condition (Sr) in place

R

fIn(22 ) C

R

SOURCE

SCL

N

IN

IN

≤

××

×

−

2

58.6ksps, 14-Bit, 2-Wire Serial ADC

in a 14-Pin TSSOP

______________________________________________________________________________________

13

Figure 5. Equivalent Input Circuit

AIN

AGNDS

CAPACITIVE

DAC

REF

HOLD

TRACK

ANALOG

SIGNAL

SOURCE

MAX1069

Figure 6. Internal Protection Diodes

AIN

REFADJ

AVDD

AGND

REF

AGNDS

MAX1069