M48Z512AV datasheet(9/21 Pages) STMICROELECTRONICS

9 / 21 page

M48Z512A, M48Z512AY, M48Z512AV

Operating modes

Doc ID 5146 Rev 8

9/21

2.2

WRITE mode

The M48Z512A/Y/V is in the WRITE mode whenever W and E are active. The start of a

WRITE is referenced from the latter occurring falling edge of W or E. A WRITE is terminated

by the earlier rising edge of W or E.

The addresses must be held valid throughout the cycle. E or W must return high for a

minimum of tEHAX from E or tWHAX from W prior to the initiation of another READ or WRITE

cycle. Data-in must be valid tDVEH or tDVWH prior to the end of WRITE and remain valid for

tEHDX or tWHDX afterward. G should be kept high during WRITE cycles to avoid bus

contention; although, if the output bus has been activated by a low on E and G, a low on W

will disable the outputs tWLQZ after W falls.

Table 3.

READ mode AC characteristics

Symbol

Parameter(1)

Valid for ambient operating temperature: TA = 0 to 70 °C or –40 to 85 °C; VCC = 4.75 to 5.5 V, 4.5 to 5.5 V,

or 3.0 to 3.6 V (except where noted).

M48Z512A/Y

–70

M48Z512A/Y/V

–85

Unit

Min

Max

Min

Max

tAVAV

READ cycle time

tAVQV

Address valid to output valid

tELQV

Chip enable low to output valid

tGLQV

Output enable low to output valid

tELQX

(2)

CL = 5 pF.

Chip enable low to output transition

tGLQX

(2)

Output enable low to output transition

tEHQZ

(2)

Chip enable high to output Hi-Z

tGHQZ

(2)

Output enable high to output Hi-Z

tAXQX

Address transition to output transition

M48Z512AV Scheda tecnica(PDF) 9 Page - STMicroelectronics

M48Z512AV Scheda tecnica(HTML) 9 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21

Scheda tecnica Scarica

Link URL