IC-NQL datasheet(11/24 Pages) ICHAUS

11 / 24 page

iC-NQL

13-bit Sin/D CONVERTER WITH SSI INTERFACE

Rev B1, Page 11/24

SIGNAL CONDITIONING

Input stages SIN and COS are conﬁgured as instru-

mentation ampliﬁers. The ampliﬁer gain must be se-

lected in accordance with the sensor signal level and

programmed to register GAIN according to the follow-

ing table. Half of the supply voltage is output to VREF

as center voltage to help DC level adaptation.

GAIN

Adr 0x08, Bit 7:4

Sine/Cosine Input Signal Levels Vin()

Amplitude

Average value (DC)

Code

Ampliﬁcation

Differential

Single-ended

Differential

Single-ended

0x0F

80.000

up to 50 mVpp

up to 100 mVpp

0.7 V ... VDDA - 1.2 V

0.8 V ... VDDA - 1.2 V

0x0E

66.667

up to 60 mVpp

up to 120 mVpp

0.7 V ... VDDA - 1.2 V

0.8 V ... VDDA - 1.2 V

0x0D

53.333

up to 75 mVpp

up to 0.15 Vpp

0.7 V ... VDDA - 1.2 V

0.8 V ... VDDA - 1.2 V

0x0C

40.000

up to 0.1 Vpp

up to 0.2 Vpp

1.2 V ... VDDA - 1.2 V

1.3 V ... VDDA - 1.3 V

0x0B

33.333

up to 0.12 Vpp

up to 0.24 Vpp

1.2 V ... VDDA - 1.2 V

1.3 V ... VDDA - 1.3 V

0x0A

28.571

up to 0.14 Vpp

up to 0.28 Vpp

0.7 V ... VDDA - 1.2 V

0.8 V ... VDDA - 1.3 V

0x09

26.667

up to 0.15 Vpp

up to 0.3 Vpp

1.2 V ... VDDA - 1.2 V

1.3 V ... VDDA - 1.3 V

0x08

20.000

up to 0.2 Vpp

up to 0.4 Vpp

0.7 V ... VDDA - 1.2 V

0.8 V ... VDDA - 1.3 V

0x07

14.287

up to 0.28 Vpp

up to 0.56 Vpp

1.2 V ... VDDA - 1.3 V

1.4 V ... VDDA - 1.4 V

0x06

10.000

up to 0.4 Vpp

up to 0.8 Vpp

1.2 V ... VDDA - 1.3 V

1.4 V ... VDDA - 1.5 V

0x05

8.000

up to 0.5 Vpp

up to 1 Vpp

0.8 V ... VDDA - 1.4 V

1.0 V ... VDDA - 1.6 V

0x04

6.667

up to 0.6 Vpp

up to 1.2 Vpp

0.8 V ... VDDA - 1.4 V

1.1 V ... VDDA - 1.7 V

0x03

5.333

up to 0.75 Vpp

up to 1.5 Vpp

0.9 V ... VDDA - 1.5 V

1.3 V ... VDDA - 1.9 V

0x02

4.000

up to 1 Vpp

up to 2 Vpp

1.2 V ... VDDA - 1.6 V

1.7 V ... VDDA - 2.1 V

0x01

3.333

up to 1.2 Vpp

up to 2.4 Vpp

1.2 V ... VDDA - 1.7 V

1.8 V ... VDDA - 2.3 V

0x00

2.667

up to 1.5 Vpp

up to 3 Vpp

1.3 V ... VDDA - 1.8 V

2.0 V ... VDDA - 2.6 V

Table 6: Gain Select

SINOFFS

Adr 0x09, Bit 7:0

COSOFFS

Adr 0x0A, Bit 7:0

Code

Output Offset

Input Offset

0x00

0 V

0x01

-7.8125 mV

-7.8125* mV / GAIN

...

0x7F

-0.9922 V

-0.9922 V / GAIN

0x80

0 V

0x81

+7,8125 mV

+7.8125 mV / GAIN

...

0xFF

+0.9922 V

+0.9922 V / GAIN

Notes

*) With REFOFFS = 0x00 und VDDA = 5 V.

Table 7: Offset Calibration Sine/Cosine

REFOFFS

Adr 0x0B, Bit 1

Code

Reference Voltage

0x00

Depending on VDDA

(example of application: MR sensors)

0x01

Not depending on VDDA

(example of application: Sin/Cos encoders)

Table 8: Offset Calibration Reference

RATIO

Adr 0x0B, Bit 0, Adr 0x08, Bit 3:0

Code

COS / SIN

Code

COS / SIN

0x00

1.0000

0x10

1.0000

0x01

1.0067

0x11

0.9933

...

0x0F

1.1

0x1F

0.9000

Table 9: Amplitude Calibration

PHASE

Adr 0x0B, Bit 7:2

Code

Phase Shift

Code

Phase Shift

0x00

90°

0x20

90°

0x01

90.703125°

0x21

89.296875°

...

0x12

102.65625°

0x32

77.34375°

...

102.65625°

...

77.34375°

0x1F

102.65625°

0x3F

77.34375°

Table 10: Phase Calibration

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