CTCSS Signalling Processor

FX818

© 1997 Consumer Microcircuits Limited

25

D/818/4

1.7.1

Electrical Performance (continued)

Timing Diagrams

Figure 4 "C-BUS" Timing

For the following conditions unless otherwise specified:

Parameter

Notes

Min.

Typ.

Max.

Units

"CS-Enable to Clock-High"

2.0

-

µs

Last "Clock-High to CS-High"

4.0

-

µs

"CS-High to Reply Output 3-state"

-

2.0

µs

"CS-High" Time between transactions

2.0

-

µs

"Inter-Byte" Time

4.0

-

µs

"Clock-Cycle" time

2.0

-

µs

Notes:

1.

Depending on the command, 1 or 2 bytes of COMMAND DATA are transmitted to the peripheral

MSB (Bit 7) first, LSB (Bit 0) last. REPLY DATA is read from the peripheral MSB (Bit 7) first, LSB

(Bit 0) last.

2.

Data is clocked into and out of the peripheral on the rising SERIAL CLOCK edge.

3.

Loaded commands are acted upon at the end of each command.

4.

To allow for differing µController serial interface formats "C-BUS" compatible ICs are able to work

with either polarity SERIAL CLOCK pulses.