GC5337 datasheet(39/49 Pages) TI

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ADC Data

ADC Frame Clock

ADC Clock

T0513-01

GC5330

GC5337

www.ti.com

SLWS226 B

– DECEMBER 2010 – REVISED JANUARY 2011

Figure 21. RX ADC LVDS Timing Specifications (RXA and RXB)

Table 21. RXA-BB Switching Characteristics

PARAMETER

TEST CONDITIONS

MIN

NOM

MAX

UNIT

fCLK(BB-A)

RX input clock frequency

See (1)

250

MHz

Input data setup time on port A before

tsu(BB-A)

See (1)(2)

160

ADCA Clk transition

Input data hold time on port A after

th(BB-A)

See (1)(2)

200

ADCA Clk transition

(1)

Chip specifications are production tested at 90

°C case temperature for the given specification. Early production lots are sample tested

–40°C.

(2)

Setup and hold times apply to data and appropriate ADC Clk, respectively. Timing is measured from ADC Clk threshold crossing.

Table 22. DPD Clock and Sync A,B Switching Characteristics(1)

PARAMETER

TEST CONDITIONS

MIN

NOM

MAX

UNIT

fCLK(DPD)

310

MHz

DPD input clock frequency

See (2)

{370}

250

fCLK(BB)

BB internal clock frequency

See (1)

MHz

{290}

tDUTY-CYCLE

DPD input clock duty cycle

See (3)

40%

60%

fCLK (JITTERRMS-DPD) DPD clock input jitter

See (3)

2.5%

tsu(SYNCA)

Input data setup time before fCLK↑

See (2)

0.25

th(SYNCA)

Input data hold time after fCLK↑

See (2)

0.1

tsu(SYNCB)

Input data setup time before fCLK↑

See (2)

0.35

th(SYNCB)

Input data hold time after fCLK↑

See (2)

0.05

(1)

The PLL output ranges are 400

–1000 MHz. These are configuration dependent but related to the DPDCLK frequency. The cmd5330

software automatically checks these limits when compiling a configuration.

(2)

Chip specifications are production tested at 90

°C case temperature for the given specification. Early production lots are sample tested

–40°C.

(3)

Specification is from the PLL specification and is not production tested.

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