LC33832PL datasheet(6/9 Pages) SANYO

6 / 9 page

LC33832P, S, M, PL, SL, ML-70/80/10

No. 4430-6/9

Continued from preceding page.

Note : 5) To accomplish internal initialization, CE and OE/RFSH are fixed at VIH for an interval of 1 ms when VCC reaches the

specified voltage after power is switched on.

6) Measured at tT = 5 ns.

7) When measuring input signal timing, VIH (min) and VIL (max) are reference levels.

8) Measured using an equivalent of 100 pF and two standard TTL loads.

9) OE/RFSH input functions as output-enable input (OE) when CE = VIL, and as refresh input (RFSH) when CE = VIH.

10) tCHZ, tOHZ, and tWHZ are defined as the time until output enters the open circuit state and the output voltage level

becomes immeasurable.

11) As with ordinary static RAM, write data is incorporated at the rise of WE input or CE input, whichever is earlier, and

write data is therefore held during tDSW, tDSC, tDHW, or tDHC.

12) Because address input is incorporated at the fall of CE, the address is maintained during tASC or tAHC.

13) Auto-refresh and self-refresh are determined by OE/RFSH pulse width when CE = VIH, and are defined as auto-refresh

when below tFAP (max), or as self-refresh when above tFAS (min). In order to activate CE after the completion of each

refresh, tFCE must be assured for auto-refresh, or tFRS must be assured for self-refresh.

LC33832PL Scheda tecnica(PDF) 6 Page - Sanyo Semicon Device