HT1621 datasheet(8/15 Pages) HOLTEK

8 / 15 page

HT1626

Rev. 1.60

November 9, 2010

PATENTED

Functional Description

Display Memory

- RAM Structure

The static display RAM is organized into 192

´4 bits and

stores the display data. The contents of the RAM are di-

rectly mapped to the contents of the LCD driver. Data in

the RAM can be accessed by the READ, WRITE and

READ-MOD-

IFY-WRITE commands. The following is a mapping from

the RAM to the LCD patterns.

Time Base and Watchdog Timer

- WDT

The time base generator and WDT share the same di-

vided (/256) counter. TIMER DIS/EN/CLR, WDT

DIS/EN/CLR and IRQ EN/DIS are independent from each

other. Once the WDT time-out occurs, the IRQ pin will

remain at logic low level until the CLR WDT or the IRQ

DIS command is issued.

If an external clock is selected as the source of system

frequency, the SYS DIS command turns out invalid and

the power down mode fails to be carried out until the ex-

ternal clock source is removed.

Buzzer Tone Output

A simple tone generator is implemented in the HT1626.

The tone generator can output a pair of differential driv-

ing signals on the BZ and BZ which are used to generate

a single tone.

Command Format

The HT1626 can be configured by the software setting.

There are two mode commands to configure the

HT1626 resource and to transfer the LCD display data.

S E G 0

S E G 1

S E G 2

S E G 3

S E G 4 7

C O M 1 2

C O M 1 3

C O M 1 4

C O M 1 5

A d d r

1 9 1

1 1

1 5

C O M 0

C O M 1

C O M 2

C O M 3

A d d r

1 8 8

1 2

D a t a 4 B i t s

( D 3 , D 2 , D 1 , D 0 )

A d d r e s s 8 B i t s

( A 7 , A 6 , . . . . , A 0 )

D 3

D 2

D 1

D 0

D a t a

D 3

D 2

D 1

D 0

D a t a

RAM Mapping

9 0 %

5 0 %

1 0 %

G N D

W R , R D

C l o c k

t f

t r

t C L K

V D D

Figure 1

5 0 %

V A L I D D A T A

5 0 %

D B

W R , R D

C l o c k

G N D

t s u

t h

V D D

G N D

Figure 2

C S

G N D

5 0 %

F I R S T

C l o c k

L A S T

C l o c k

G N D

W R , R D

C l o c k

t s u 1

t h 1

t C S

V D D

Figure 3

t S R

t O F F

V D D

0 V

C S

0 . 9 V D D

t R S T D

Figure 4. Power-on Reset Timing

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