R5F2136CMNFD datasheet(56/61 Pages) RENESAS

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R8C/36M Group

5. Electrical Characteristics

Under development Preliminary document

Specifications in this document are tentative and subject to change.

R01DS0086EJ0010 Rev.0.10

Page 56 of 58

Mar 09, 2011

i = 0 to 2

Figure 5.21

Serial Interface Timing Diagram when VCC = 2.2 V

Notes:

1. When selecting the digital filter by the INTi input filter select bit, use an INTi input HIGH width of either (1/digital filter clock

frequency × 3) or the minimum value of standard, whichever is greater.

2. When selecting the digital filter by the INTi input filter select bit, use an INTi input LOW width of either (1/digital filter clock

frequency × 3) or the minimum value of standard, whichever is greater.

Figure 5.22

Input Timing Diagram for External Interrupt INTi and Key Input Interrupt KIi

when VCC = 2.2 V

Table 5.37

Serial Interface

Symbol

Parameter

Standard

Unit

Min.

Max.

tc(CK)

CLKi input cycle time

When external clock is selected

800

−

tW(CKH)

CLKi input “H” width

400

−

tW(CKL)

CLKi input “L” width

400

−

td(C-Q)

TXDi output delay time

−

200

th(C-Q)

TXDi hold time

−

tsu(D-C)

RXDi input setup time

150

−

th(C-D)

RXDi input hold time

−

td(C-Q)

TXDi output delay time

When internal clock is selected

−

200

tsu(D-C)

RXDi input setup time

150

−

th(C-D)

RXDi input hold time

−

Table 5.38

External Interrupt INTi (i = 0 to 4) Input, Key Input Interrupt KIi (i = 0 to 3)

Symbol

Parameter

Standard

Unit

Min.

Max.

tW(INH)

INTi input “H” width, KIi input “H” width

1000 (1)

—ns

tW(INL)

INTi input “L” width, KIi input “L” width

1000 (2)

—ns

tW(CKH)

tC(CK)

tW(CKL)

th(C-Q)

th(C-D)

tsu(D-C)

td(C-Q)

CLKi

TXDi

RXDi

VCC = 2.2 V

i = 0 to 2

tW(INL)

tW(INH)

VCC = 2.2 V

INTi input

(i = 0 to 4)

KIi input

(i = 0 to 3)

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