PIC16F1946 datasheet(304/448 Pages) MICROCHIP

304 / 448 page

PIC16(L)F1946/1947

DS41414C-page 304

Preliminary

 2010-2011 Microchip Technology Inc.

25.1.2.8

Asynchronous Reception Set-up:

Initialize the SPxBRGH:SPxBRGL register pair

and the BRGH and BRG16 bits to achieve the

desired baud rate (see Section 25.4 “EUSART

Baud Rate Generator (BRG)”

Set the RXx/DTx and TXx/CKx TRIS controls to

‘1’.

Enable the serial port by setting the SPEN bit

and the RXx/DTx pin TRIS bit. The SYNC bit

must be clear for asynchronous operation.

If interrupts are desired, set the RCxIE interrupt

enable bit and set the GIE and PEIE bits of the

INTCON register.

If 9-bit reception is desired, set the RX9 bit.

Enable reception by setting the CREN bit.

The RCxIF interrupt flag bit will be set when a

character is transferred from the RSR to the

receive buffer. An interrupt will be generated if

the RCxIE interrupt enable bit was also set.

Read the RCxSTA register to get the error flags

and, if 9-bit data reception is enabled, the ninth

data bit.

Get the received 8 Least Significant data bits

from the receive buffer by reading the RCxREG

10. If an overrun occurred, clear the OERR flag by

clearing the CREN receiver enable bit.

25.1.2.9

9-bit Address Detection Mode Set-up

This mode would typically be used in RS-485 systems.

To set up an Asynchronous Reception with Address

Detect Enable:

Initialize the SPxBRGH, SPxBRGL register pair

and the BRGH and BRG16 bits to achieve the

desired baud rate (see Section 25.4 “EUSART

Baud Rate Generator (BRG)”

Set the RXx/DTx and TXx/CKx TRIS controls to

‘1’.

Enable the serial port by setting the SPEN bit.

The SYNC bit must be clear for asynchronous

operation.

If interrupts are desired, set the RCxIE interrupt

enable bit and set the GIE and PEIE bits of the

INTCON register.

Enable 9-bit reception by setting the RX9 bit.

Enable address detection by setting the ADDEN

bit.

Enable reception by setting the CREN bit.

The RCxIF interrupt flag bit will be set when a

character with the ninth bit set is transferred

from the RSR to the receive buffer. An interrupt

will be generated if the RCxIE interrupt enable

bit was also set.

Read the RCxSTA register to get the error flags.

The ninth data bit will always be set.

10. Get the received 8 Least Significant data bits

from the receive buffer by reading the RCxREG

device’s address.

11. If an overrun occurred, clear the OERR flag by

clearing the CREN receiver enable bit.

12. If the device has been addressed, clear the

ADDEN bit to allow all received data into the

receive buffer and generate interrupts.

FIGURE 25-5:

ASYNCHRONOUS RECEPTION

Start

bit

bit 7/8

bit 1

bit 0

bit 7/8

bit 0

Stop

bit

Start

bit

Start

bit

bit 7/8 Stop

bit

RXx/DTx pin

Reg

Rcv Buffer Reg

Rcv Shift

Read Rcv

Buffer Reg

RCxREG

RCxIF

(Interrupt Flag)

OERR bit

CREN

Word 1

RCxREG

Word 2

RCxREG

Stop

bit

Note:

This timing diagram shows three words appearing on the RXx/DTx input. The RCxREG (receive buffer) is read after the third

word, causing the OERR (overrun) bit to be set.

RCIDL

PIC16F1946 Scheda tecnica(PDF) 304 Page - Microchip Technology

PIC16F1946 Scheda tecnica(HTML) 304 Page - Microchip Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Scheda tecnica Scarica

Link URL