PIC16F1946 datasheet(303/448 Pages) MICROCHIP

303 / 448 page

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Preliminary

DS41414C-page 303

PIC16(L)F1946/1947

25.1.2.3

Receive Interrupts

The RCxIF interrupt flag bit of the PIR1/PIR3 register is

set whenever the EUSART receiver is enabled and

there is an unread character in the receive FIFO. The

RCxIF interrupt flag bit is read-only, it cannot be set or

cleared by software.

RCxIF interrupts are enabled by setting the following

bits:

• RCxIE interrupt enable bit of the PIE1/PIE3

• PEIE peripheral interrupt enable bit of the INTCON

• GIE global interrupt enable bit of the INTCON

The RCxIF interrupt flag bit will be set when there is an

unread character in the FIFO, regardless of the state of

interrupt enable bits.

25.1.2.4

Receive Framing Error

Each character in the receive FIFO buffer has a

corresponding framing error Status bit. A framing error

indicates that a Stop bit was not seen at the expected

time. The framing error status is accessed via the

FERR bit of the RCxSTA register. The FERR bit

represents the status of the top unread character in the

receive FIFO. Therefore, the FERR bit must be read

before reading the RCxREG.

The FERR bit is read-only and only applies to the top

unread character in the receive FIFO. A framing error

(FERR = 1) does not preclude reception of additional

characters. It is not necessary to clear the FERR bit.

Reading the next character from the FIFO buffer will

advance the FIFO to the next character and the next

corresponding framing error.

The FERR bit can be forced clear by clearing the SPEN

bit of the RCxSTA register which resets the EUSART.

Clearing the CREN bit of the RCxSTA register does not

affect the FERR bit. A framing error by itself does not

generate an interrupt.

25.1.2.5

Receive Overrun Error

The receive FIFO buffer can hold two characters. An

overrun error will be generated If a third character, in its

entirety, is received before the FIFO is accessed. When

this happens the OERR bit of the RCxSTA register is

set. The characters already in the FIFO buffer can be

read but no additional characters will be received until

the error is cleared. The error must be cleared by either

clearing the CREN bit of the RCxSTA register or by

resetting the EUSART by clearing the SPEN bit of the

RCxSTA register.

25.1.2.6

Receiving 9-bit Characters

The EUSART supports 9-bit character reception. When

the RX9 bit of the RCxSTA register is set, the EUSART

will shift 9 bits into the RSR for each character

received. The RX9D bit of the RCxSTA register is the

ninth and Most Significant data bit of the top unread

character in the receive FIFO. When reading 9-bit data

from the receive FIFO buffer, the RX9D data bit must

be read before reading the 8 Least Significant bits from

the RCxREG.

25.1.2.7

Address Detection

A special Address Detection mode is available for use

when multiple receivers share the same transmission

line, such as in RS-485 systems. Address detection is

enabled by setting the ADDEN bit of the RCxSTA

Address detection requires 9-bit character reception.

When address detection is enabled, only characters

with the ninth data bit set will be transferred to the

receive FIFO buffer, thereby setting the RCxIF interrupt

bit. All other characters will be ignored.

Upon receiving an address character, user software

determines if the address matches its own. Upon

address match, user software must disable address

detection by clearing the ADDEN bit before the next

Stop bit occurs. When user software detects the end of

the message, determined by the message protocol

used, software places the receiver back into the

Address Detection mode by setting the ADDEN bit.

Note:

If all receive characters in the receive

FIFO have framing errors, repeated reads

of the RCxREG will not clear the FERR

bit.

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