DAC7562 datasheet(6/56 Pages) TI1

6 / 56 page

OUT

GND

LDAC

CLR

SYNC

SCLK

REFIN

REFOUT

REFIN

REFOUT

OUT

GND

LDAC

CLR

DGS

(Top View)

DSC

(Top View)

MSOP Package

QFN Package

Thermal Pad

(1)

DAC8562, DAC8563

DAC8162, DAC8163

DAC7562, DAC7563

SLAS719C

– AUGUST 2010 – REVISED JUNE 2011

www.ti.com

PIN CONFIGURATIONS

(1)

It is recommended to connect the thermal pad to the ground plane for better thermal dissipation.

Table 2. PIN DESCRIPTIONS

DESCRIPTION

NAME

NO.

AVDD

Power-supply input, 2.7 V to 5.5 V

Asynchronous clear input. The CLR input is falling-edge sensitive. When CLR is activated, zero scale

(DACxx62) or mid-scale (DACxx63) is loaded to all input and DAC registers. This sets the DAC output

CLR

voltages accordingly. The part exits clear code mode on the 24th falling edge of the next write to the part. If

CLR is activated during a write sequence, the write is aborted.

Serial data input. Data are clocked into the 24-bit input shift register on each falling edge of the serial clock

DIN

input. Schmitt-trigger logic input

GND

Ground reference point for all circuitry on the device

In synchronous mode, data are updated with the falling edge of the 24th SCLK cycle, which follows a falling

edge of SYNC. For such synchronous updates, the LDAC pin is not required, and it must be connected to

GND permanently or asserted and held low before sending commands to the device.

LDAC

In asynchronous mode, the LDAC pin is used as a negative edge-triggered timing signal for simultaneous

DAC updates. Multiple single-channel commands can be written in order to set different channel buffers to

desired values and then make a falling edge on LDAC pin to simultaneously update the DAC output

registers.

SCLK

Serial clock input. Data can be transferred at rates up to 50 MHz. Schmitt-trigger logic input

Level-triggered control input (active-low). This input is the frame synchronization signal for the input data.

When SYNC goes low, it enables the input shift register, and data are sampled on subsequent falling clock

SYNC

edges. The DAC output updates following the 24th clock falling edge. If SYNC is taken high before the 23rd

clock edge, the rising edge of SYNC acts as an interrupt, and the write sequence is ignored by the

DAC756x/DAC816x/DAC856x. Schmitt-trigger logic input

VOUTA

Analog output voltage from DAC-A

VOUTB

Analog output voltage from DAC-B

VREFIN / VREFOUT

Bidirectional voltage reference pin. If internal reference is used, 2.5-V output.

Submit Documentation Feedback

Product Folder Link(s): DAC8562 DAC8563 DAC8162 DAC8163 DAC7562 DAC7563

DAC7562 Scheda tecnica(PDF) 6 Page - Texas Instruments

DAC7562 Scheda tecnica(HTML) 6 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56

Scheda tecnica Scarica

Link URL