Technical Note

7/14

BU95101

www.rohm.com

2010.10 - Rev.A

© 2010 ROHM Co., Ltd. All rights reserved.

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Pin descriptions

Pin Name

In/Out

Active

Descriptions

In

Differential

RSDS input terminals of display data

The 3-bit differential input pairs generate the internal 6-bit data through the

In

Differential The RSDS clock input pair generate the internal shift clock through the

Y1 ~ Y384

Out

-

Driver outputs for D/A converted 64 gray scale analog voltage.

R/L

In

-

The shift direction of internal shift register is controlled by this pin as shown below.

R/L=H : Right shift SFTR→Y1→Y384→SFTL

R/L=L : Left shift SFTL→Y384→Y1→SFTR

SFTR

In/Out

H

SFTR=H：Right shift start pulse input terminal in cascade connection.

SFTR=L：Carry output terminal in cascade connection.

SFTL

In/Out

H

SFTL=H：Carry output terminal in cascade connection.

SFTL=L：Left shift start pulse input terminal in cascade connection.

STB

In

The data in the data register are transferred to the data latch at the rising edge

of STB, then the gray scale voltages are output from the buffer at the falling

edge of STB.

INV

In

H

Terminal to specify inverting or non-inverting of display data

INV:H : Input data are inverted in the IC.

INV:L : Input data are not inverted.

V1 ~ V10

In

-

Input for the γ-correction reference voltage

The following external reference voltages are input.

POL

In

-

At the rising edge of STB, the state of POL are transferred to the driver.

POL=H : The reference voltage for odd number outputs are V1 to V5

and those for even number outputs are V6 to V10.

POL=L : The reference voltage for odd number outputs are V6 to V10

and those for even number outputs are V1 to V5

IREP1,2

In

-

Repair amplifier input

OREP1,2

Out

-

Repair amplifier output

In

-

Power supply for driver block

In

-

In

-

Power supply for digital block

In

-