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ICS9220 Scheda tecnica(PDF) 7 Page - Integrated Device Technology |
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ICS9220 Scheda tecnica(HTML) 7 Page - Integrated Device Technology |
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7 / 17 page ![]() 7 ICS9220 1227G—11/05/07 PLL Multiplier Table 2 shows the frequency multipliers in the PLL, selectable by programming the MULT0, MULT1 and MULT2 bits in the SMBus Multiplier Control register. Power up default is 4. Table 2. PLL Multiplier Programming Selection 46 8 300.00000 4 1200.0000 6 18 84 10 1200.00 1800.00 2400.00 325.00000 4 1300.0000 4 13 82 0B 1300.00 1950.00 2600.00 350.00000 4 1400.0000 6 21 84 13 1400.00 2100.00 2800.00 366.66667 4 1466.6667 6 22 84 14 1466.67 2200.00 2933.33 375.00000 4 1500.0000 4 15 82 0D 1500.00 2250.00 3000.00 383.33333 4 1533.3333 6 23 84 15 1533.33 2300.00 3066.67 400.00000 4 1600.0000 6 24 84 16 1600.00 2400.00 3200.00 416.66667 4 1666.6667 6 25 84 17 1666.67 2500.00 3333.33 425.00000 2 850.0000 4 17 02 0F 1700.00 2550.00 3400.00 433.33333 2 866.6667 6 26 04 18 1733.33 2600.00 3466.67 450.00000 2 900.0000 6 27 04 19 1800.00 2700.00 3600.00 466.66667 2 933.3333 6 28 04 1A 1866.67 2800.00 3733.33 475.00000 2 950.0000 4 19 02 11 1900.00 2850.00 3800.00 483.33333 2 966.6667 6 29 04 1B 1933.33 2900.00 3866.67 500.00000 2 1000.0000 6 30 04 1C 2000.00 3000.00 4000.00 516.66667 2 1033.3333 6 31 04 1D 2066.67 3100.00 4133.33 533.33333 2 1066.6667 6 32 04 1E 2133.33 3200.00 4266.67 550.00000 2 1100.0000 6 33 04 1F 2200.00 3300.00 4400.00 566.66667 2 1133.3333 6 34 04 20 2266.67 3400.00 4533.33 583.33333 2 1166.6667 6 35 04 21 2333.33 3500.00 4666.67 600.00000 2 1200.0000 6 36 04 22 2400.00 3600.00 4800.00 616.66667 2 1233.3333 6 37 04 23 2466.67 3700.00 4933.33 633.33333 2 1266.6667 6 38 04 24 2533.33 3800.00 5066.67 650.00000 2 1300.0000 6 39 04 25 2600.00 3900.00 5200.00 666.66667 2 1333.3333 6 40 04 26 2666.67 4000.00 5333.33 NOTE: Byte 5 Hex Byte 6 Hex ASIC Multiplier All output values based on 100.000000MHz input clock PostDiv B5b7 VCO M B5b(3:0) N B6b(5:0) OUTPUT |
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