SAM3U datasheet(49/59 Pages) ATMEL

49 / 59 page

6430ES–ATARM–22-Aug-11

SAM3U Series

– Pulse Generation

–Delay Timing

– Pulse Width Modulation

– Up/Down Capabilities

– Quadrature Decoder Logic

• Each channel is user-configurable and contains:

– Three external clock inputs

– Five internal clock inputs

– Two multi-purpose input/output signals

• Two global registers that act on all three TC Channels

12.7

Pulse Width Modulation Controller (PWM)

• 4 channels, one 16-bit counter per channel

• Common clock generator, providing Thirteen Different Clocks

– A Modulo n counter providing eleven clocks

– Two independent Linear Dividers working on modulo n counter outputs

– High Frequency Asynchronous clocking mode

• Independent channel programming

– Independent Enable Disable Commands

– Independent Clock Selection

– Independent Period and Duty Cycle, with Double Buffering

– Programmable selection of the output waveform polarity

– Programmable center or left aligned output waveform

– Independent Output Override for each channel

– Independent complementary Outputs with 12-bit dead time generator for each

channel

– Independent Enable Disable Commands

– Independent Clock Selection

– Independent Period and Duty Cycle, with Double Buffering

• Synchronous Channel mode

– Synchronous Channels share the same counter

– Mode to update the synchronous channels registers after a programmable number

of periods

• Connection to one PDC channel

– Offers Buffer transfer without Processor Intervention, to update duty cycle of

synchronous channels

• Two independent event lines which can send up to 8 triggers on ADC within a period

• Four programmable Fault Inputs providing asynchronous protection of outputs

SAM3U Scheda tecnica(PDF) 49 Page - ATMEL Corporation