Specifications subject to change without notice. All dimensions in inches. © Copyright 2011 The Connor-Winfield Corporation

2111 Comprehensive Drive

Aurora, Illinois 60505

Phone: 630- 851- 4722

Fax: 630- 851- 5040

www.conwin.com

Suggested Pad Layout

Design Recommendations

Output Waveform

Tape and Reel Dimensions

1:

Do Not Connect

2:

Do Not Connect

3:

Do Not Connect

4:

Ground

5:

Output

6:

Do Not Connect

7:

Do Not Connect

8:

Tri-State Enable / Disable

9:

Supply Voltage Vcc

10:

N/C

Pad Connections

Solder Profile

120°C

150°C

180°C

260°C

0

220°C

Up to 120 s

Typical

10 s

60 to 90 s

Typical

Temperature

260°C

Meets IPC/JEDEC J-STD-020C

120°C

150°C

180°C

260°C

0

220°C

Up to 120 s

Typical

10 s

60 to 90 s

Typical

Temperature

260°C

Meets IPC/JEDEC J-STD-020C

Package Layout

200 mV/Div

0

0.276

0.006

(7.0mm)

±

0.197

0.006

(5.0mm)

±

0.079 Max.

(2.0mm)

D75AS 1144

20.0 MHZ

0.025(6 Places)

(0.635mm)

0.100

(2.54mm)

0.040

(1.02mm)

(6 Places)

0.030

(0.762mm)

(4 Places)

0.100

(2.54mm)

Pin 1

0.038

(0.965mm)

(4 Places)

Dimensional Tolerance:

±.005 (.127mm)

±.02

(.508mm)

1

2

3

4

5

6

7

8

9

10

Bottom

View

MEETS EIA-481A and EIAJ-1009B

2,000 PCS/REEL

8.46 DIA

(216mm DIA)

.08

(2.0mm)

1.00 DIA

(25mm DIA)

9.84 DIA

(250mm DIA)

.06 DIA

(1.5mm DIA)

.69

(17.5mm)

.08

(2.0mm)

3.15

(80mm)

.315

(8.0mm)

.08

(2.0mm)

.21

(5.4mm)

.157

(4.0mm)

.31

(7.9mm)

.295 (7.5mm)

.07 (1.75mm)

.83 (16.0mm)

PIN 1

Direction

Of

Feed

(Customer)

0.215

(5.46mm)

0.037

(0.94mm)

0.051

(1.28mm)

0.051

(1.28mm)

0.295

(7.49mm)

0.030

(0.76mm)

Keep Out Area

Top View

1

10

9

5

4

8

2

3

6

7

* Do not route any traces in the keep out area. It is

recommended the next layer under the keep out

area is to be ground plane.

4

5

1

2

3

6

7

8

9

10

Vcc

Supply

Voltage

N/C

DNC

DNC DNC

DNC DNC

10 nF

Bypass

Enable/

Disable

Output

10 pF

Ground

0.1 uF

Bypass

DNC = Do Not Connect

10K

Ohm

OSC

TOP LAYER

GROUND LAYER

BOTTOM LAYER

Output

Buffer

50 Ohm Trace

Without

Vias

Vcc, should have

a large copper

area for reduced

inductance.

Connect a 0.01uF

bypass capacitor

<0.1”(2.54mm)

from the pad.

Ground,

should have

a large copper

area for reduced

inductance.

0.010”(0.254mm)

Recommended

clearance

inductance

for internal

copper flood.

Top View

1

3

4

5

6

8

9

10

Buffer

Ground

50 Ohm trace

<1”by design

Vcc

Ground

Top View

Test Circuit

Attention: To achieve optimal frequency stability, and in some cases to meet the specification stated on this data

sheet, it is required that the circuit connected to this TCXO output must have the equivalent input capacitance

that is specified by the nominal load capacitance. Deviations from the nominal load capacitance will have a

graduated effect on the stability of approximately 20 ppb per pF load difference.

Bulletin

Tx243

Page

2 of 2

Revision

02

Date

03 Nov 2011