AD9608 datasheet(13/40 Pages) AD

13 / 40 page

AD9608

Rev. 0 | Page 13 of 40

PIN 1

INDICATOR

D6+

D6–

D7+

D7–

CLK+

CLK–

SYNC

DRVDD

PDWN

OEB

CSB

SCLK/DFS

SDIO/DCS

OR+

OR–

DRVDD

D9+ (MSB)

D9– (MSB)

D8+

D8–

AD9608

INTERLEAVED PARALLEL LVDS

TOP VIEW

(Not to Scale)

NOTES

1. NC = NO CONNECT. DO NOT CONNECT TO THIS PIN.

2. THE EXPOSED THERMAL PAD ON THE BOTTOM OF THE PACKAGE PROVIDES

THE ANALOG GROUND FOR THE PART. THIS EXPOSED PAD MUST BE

CONNECTED TO GROUND FOR PROPER OPERATION.

Figure 7. Interleaved Parallel LVDS Pin Configuration (Top View)

Table 9. Pin Function Descriptions (Interleaved Parallel LVDS Mode)

Pin No.

Mnemonic

Type

Description

ADC Power Supplies

10, 19, 28, 37

DRVDD

Supply

Digital Output Driver Supply (1.8 V Nominal).

49, 50, 53, 54,

59, 60, 63, 64

AVDD

Supply

Analog Power Supply (1.8 V Nominal).

4, 5, 6, 7, 8, 9,

11, 12, 13, 14,

15, 16

No Connect. Do not connect to this pin.

AGND,

Exposed Pad

Ground

The exposed thermal pad on the bottom of the package provides the analog ground for

the part. This exposed pad must be connected to ground for proper operation.

ADC Analog

VIN+A

Input

Differential Analog Input Pin (+) for Channel A.

VIN−A

Input

Differential Analog Input Pin (−) for Channel A.

VIN+B

Input

Differential Analog Input Pin (+) for Channel B.

VIN−B

Input

Differential Analog Input Pin (−) for Channel B.

VREF

Input/Output

Voltage Reference Input/Output.

SENSE

Input

Reference Mode Selection.

RBIAS

Input/Output

External Reference Bias Resistor.

VCM

Output

Common-Mode Level Bias Output for Analog Inputs.

CLK+

Input

ADC Clock Input—True.

CLK−

Input

ADC Clock Input—Complement.

Digital Input

SYNC

Input

Digital Synchronization Pin. Slave mode only.

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