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MPC5125 Scheda tecnica(PDF) 73 Page - Freescale Semiconductor, Inc |
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MPC5125 Scheda tecnica(HTML) 73 Page - Freescale Semiconductor, Inc |
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73 / 94 page ![]() Electrical and Thermal Characteristics MPC5125 Microcontroller Data Sheet, Rev. 4 Freescale Semiconductor 73 Figure 37. Timing Diagram — I2C Input/Output 4.3.14 J1850 See the MPC5125 Reference Manual (MPC5125RM). 4.3.15 PSC The programmable serial controllers (PSC) support different modes of operation (UART, codec, AC97, SPI). All the timing numbers specified for different PSC modes are design targets. 4.3.15.1 Codec Mode (8-, 16-, 24-, and 32-Bit) / I2S Mode Table 39. Timing Specifications — 8-, 16-, 24-, and 32-Bit CODEC/I2S Master Mode1 NOTES: 1 Output timing is specified at a nominal 50 pF load. Sym Description Min Typ Max Units SpecID 1 Bit clock cycle time, programmed in CCS register 40.0 — — ns A20.1 2 Clock duty cycle 45 50 55 %2 2 Bit clock cycle time. A20.2 3 Bit clock fall time — — 7.9 ns A20.3 4 Bit clock rise time — — 7.9 ns A20.4 5 FrameSync valid after clock edge — — 8.4 ns A20.5 6 FrameSync invalid after clock edge — — 8.4 ns A20.6 7 Output data valid after clock edge — — 9.3 ns A20.7 8 Input data setup time 6.0 — — ns A20.8 1 2 3 4 5 6 78 9 SCL SDA |
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