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LD6806 Scheda tecnica(PDF) 13 Page - NXP Semiconductors |
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LD6806 Scheda tecnica(HTML) 13 Page - NXP Semiconductors |
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13 / 36 page ![]() LD6806_SER All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 3 — 9 December 2011 13 of 36 NXP Semiconductors LD6806 series Ultra low-dropout regulator, low noise, 200 mA 9.6 Load regulation Load regulation is the capability of the circuit to maintain the nominal output voltage while varying the output load current. (1) VIN (2) VOUT (1) VIN (2) VOUT Fig 21. Line regulation for LD6806CX4/36H Fig 22. Line regulation for LD6806F/36H time (ms) 0 0.8 0.6 0.2 0.4 001aan937 2 4 6 VIN (V) 0 3.55 3.65 3.75 VOUT (V) 3.45 (1) (2) time (ms) 0 0.7 0.6 0.2 0.4 0.1 0.3 0.5 001aan938 2 4 6 VIN (V) 0 3.55 3.65 3.75 VOUT (V) 3.45 (1) (2) Load regulation % mA V OUT V O nom ------------------- 100 I OUT max ----------------------------------- = (1) IOUT (2) VOUT (1) IOUT (2) VOUT Fig 23. Load regulation for LD6806CX4/12H Fig 24. Load regulation for LD6806F/12H time (ms) 0 0.2 0.4 0.6 0.7 0.5 0.3 0.1 001aan927 0.1 0.3 0.5 IOUT (A) -0.1 0.9 1.2 0.7 1.1 1.3 VOUT (V) 0.5 0.8 0.6 1.0 (1) (2) time (ms) 0 0.8 0.6 0.2 0.4 001aan928 0.1 0.3 0.5 IOUT (A) -0.1 1.10 1.25 1.00 1.20 1.30 VOUT (V) 0.90 1.05 0.95 1.15 (1) (2) |
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