HT46R92 datasheet(33/61 Pages) HOLTEK

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HT46R92

Rev. 1.10

November 5, 2008

Interrupts

Interrupts are an important part of any microcontroller

system. When an external event or an internal function

such as a Timer/Event Counter, Time Base or A/D con-

verter requires microcontroller attention, their corre-

sponding interrupt will enforce a temporary suspension

of the main program allowing the microcontroller to di-

rect attention to their respective needs. Each device in

this series contains a single external interrupt and sev-

eral internal interrupts functions. The external interrupt

is controlled by the action of the external INT pin, while

the internal interrupts are controlled by the Timer/Event

Counter overflow, Time Base overflow interrupt and the

A/D converter interrupt.

Interrupt Registers

Overall interrupt control, which means interrupt enabling

and request flag setting, is controlled by the INTC0 and

INTC1 registers, which are located in the Data Memory.

By controlling the appropriate enable bits in this register

each individual interrupt can be enabled or disabled.

Also when an interrupt occurs, the corresponding re-

quest flag will be set by the microcontroller. The global

enable flag if cleared to zero will disable all interrupts.

I N T C 1 R e g i s t e r

b 7

b 0

E A D I

A / D C o n v e r t e r i n t e r r u p t e n a b l e

1 : e n a b l e

0 : d i s a b l e

N o t i m p l e m e n t e d , r e a d a s " 0 "

A / D c o n v e r t e r i n t e r r u p t r e q u e s t f l a g

1 : a c t i v e

0 : i n a c t i v e

N o t i m p l e m e n t e d , r e a d a s " 0 "

A D F

Interrupt Control 1 Registers

I N T C 0 R e g i s t e

M a s t e r i n t e r r u p t g l o b a l e n a b l e

1 : g l o b a l e n a b l e

0 : g l o b a l d i s a b l e

E x t e r n a l i n t e r r u p t e n a b l e

1 : e n a b l e

0 : d i s a b l e

T i m e r / E v e n t C o u n t e r i n t e r r u p t e n a b l e

1 : e n a b l e

0 : d i s a b l e

T i m e B a s e i n t e r r u p t e n a b l e

1 : e n a b l e

0 : d i s a b l e

E x t e r n a l i n t e r r u p t r e q u e s t f l a g

1 : a c t i v e

0 : i n a c t i v e

T i m e r / E v e n t C o u n t e r i n t e r r u p t r e q u e s t f l a g

1 : a c t i v e

0 : i n a c t i v e

T i m e B a s e i n t e r r u p t r e q u e s t f l a g

1 : a c t i v e

0 : i n a c t i v e

F o r t e s t m o d e u s e d o n l y

M u s t b e w r i t t e n a s " 0 " ; o t h e r w i s e m a y r e s u l t i n u n p r e d i c t a b l e o p e r a t i o n

b 7

b 0

E E I

E M I

E I F

T F

E T I

E T B I

T B F

Interrupt Control 0 Registers

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