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MAX14821

IO-Link Device Transceiver

SPI Interface

The device communicates through an SPI-compatible

4-wire serial interface. The interface has three inputs—

clock (SCLK), chip select (CS), and data in (SDI)—and

one output, data out (SDO). The maximum SPI clock rate

for the device is 12MHz. The SPI interface complies with

clock polarity CPOL = 0 and clock phase CPHA = 0 (see

Figure 10 and Figure 11).

present.

Figure 10. SPI Write Cycle

Figure 11. SPI Read Cycle

R0

D7

D6

D5

D4

D3

D2

D1

D0

SCLK

R_ = REGISTER ADDRESS

D_ = DATA BIT

= CLOCK EDGE WHEN LOGIC IS LATCHED

SDI

W

00000

R1

CS

SDI

SDO

SCLK

RR1R0

00

X

X

00

0

CS

D7

D6

D5

D4

D3

D2

D1

D0

R_ = REGISTER ADDRESS

D_ = DATA BIT

= CLOCK EDGE WHEN LOGIC IS LATCHED

= CLOCK EDGE AT WHICH LOGIC IS WRITTEN