TCS3471

COLOR LIGHT-TO-DIGITAL CONVERTER

TAOS115 − MARCH 2011

13

The LUMENOLOGY

r Company

r

r

Copyright

E 2011, TAOS Inc.

www.taosinc.com

Enable Register (0x00)

The Enable register is used primarily to power the TCS3471 device on and off, and enable functions and

interrupts as shown in Table 3.

Table 3. Enable Register

6

75

4

PON

2

31

0

ENABLE

Reserved

AIEN

Address

0x00

AEN

WEN

Reserved

FIELD

BITS

DESCRIPTION

Reserved

7:5

Reserved. Write as 0.

AIEN

4

RGBC interrupt enable. When asserted, permits RGBC interrupts to be generated.

WEN

3

Wait enable. This bit activates the wait feature. Writing a 1 activates the wait timer. Writing a 0 disables the

wait timer.

Reserved

2

Reserved. Write as 0.

AEN

1

RGBC enable. This bit actives the two-channel ADC. Writing a 1 activates the RGBC. Writing a 0 disables

the RGBC.

0

Power ON. This bit activates the internal oscillator to permit the timers and ADC channels to operate.

interface, this bit is temporarily overridden and the oscillator is enabled, independent of the state of PON.

NOTE 1: A minimum interval of 2.4 ms must pass after PON is asserted before an RGBC can be initiated.

RGBC Timing Register (0x01)

The RGBC timing register controls the internal integration time of the RGBC clear and IR channel ADCs in

2.4-ms increments. Max RGBC Count = (256 − ATIME)

Table 4. RGBC Timing Register

FIELD

BITS

DESCRIPTION

ATIME

7:0

VALUE

INTEG_CYCLES

TIME

MAX COUNT

0xFF

1

2.4 ms

1024

0xF6

10

24 ms

10240

0xD5

42

101 ms

43008

0xC0

64

154 ms

65535

0x00

256

700 ms

65535

Wait Time Register (0x03)

Wait time is set 2.4 ms increments unless the WLONG bit is asserted, in which case the wait times are 12

×

longer. WTIME is programmed as a 2’s complement number.

Table 5.

Wait Time Register

FIELD

BITS

DESCRIPTION

WTIME

7:0

REGISTER VALUE

WAIT TIME

TIME (WLONG = 0)

TIME (WLONG = 1)

0xFF

1

2.4 ms

0.029 sec

0xAB

85

204 ms

2.45 sec

0x00

256

614 ms

7.4 sec