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CDCUN1208LP Scheda tecnica(PDF) 33 Page - Texas Instruments

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Il numero della parte CDCUN1208LP
Spiegazioni elettronici  400 MHz Low Power 2:8 Fan-Out Buffer
PDF  43 Pages
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Produttore elettronici  TI [Texas Instruments]
Homepage  http://www.ti.com
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CDCUN1208LP Scheda tecnica(HTML) 33 Page - Texas Instruments

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WRITE
Word
READ
Word
Slave Drives SDA
Master Drives SDA
S
T
A
R
T
I2C Address
A
C
K
7 Bits
Slave Address
7 Bits
Data
(High Byte)
B
L
O
C
K
0
W
R
I
T
E
0
A
C
K
Data
(Low Byte)
S
T
O
P
A
C
K
A
C
K
S
T
A
R
T
I2C Address
A
C
K
7 Bits
Slave Address
7 Bits
A
C
K
Data
(High Byte)
R
E
A
D
1
B
L
O
C
K
0
W
R
I
T
E
0
A
C
K
S
T
O
P
S
T
A
R
T
I2C Address
7 Bits
A
C
K
A
C
K
Data
(Low Byte)
A
C
K
S
T
O
P
CDCUN1208LP
www.ti.com
SCAS928 – MAY 2012
CDCUN1208LP Device Addressing (Register Address)
Likewise, Figure 38 shows the format of the register address field of the I2C message. The first bit determines if
the transfer is a byte or a block (more than one byte). The CDCUN1208LP register width is 16 bits (2 bytes),
therefore, generally block addressing is used to access each register in its entirety. Because the I2C protocol
requires that the slave address is a 7-bit field, the leading 3-bits are all ‘0’ while the trailing 4-bits specify the
device register of interest.
I2C Master/Slave Handshaking
Figure 39 shows the handshaking between the master (host) and the slave (CDCUN1208LP) that the I2C
protocol supports. In all cases, the master drives the SCL (clock line); however, depending on the direction of
transfer/acknowledgement, the master or the slave device drives SDA (data line).
Figure 39. I2C Master/Slave Handshaking Example
Block Read/Write
For “Block Write/Read” operations, the bytes are accessed in sequential order from lowest to highest byte (with
most significant bit first) with the ability to stop after any complete byte has been transferred. The start address of
the transfer is specified in the same way a single word transfer is initiated.
Copyright © 2012, Texas Instruments Incorporated
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