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TSU6111ARSVR Scheda tecnica(PDF) 3 Page - Texas Instruments |
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TSU6111ARSVR Scheda tecnica(HTML) 3 Page - Texas Instruments |
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3 / 32 page ![]() 16 15 14 13 DM_HOST 1 12 GND DP_HOST 2 11 SDA TxD 3 10 SCL RxD 4 9 INTB 5 6 7 8 TSU6111A www.ti.com SCDS331 – FEBRUARY 2012 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. PINOUT DIAGRAM (TOP VIEW) PIN FUNCTIONS PIN I/O DESCRIPTION NO. NAME 1 DM_HOST I/O USB DM connected to host 2 DP_HOST I/O USB DP connected to host 3 TxD I/O UART Tx 4 RxD I/O UART Rx 5 VBAT I Connected to battery 6 BOOT O BOOT mode out (push-pull). Used for factory test modes. 7 JIG O JIG detection JIG detection (Open-drain). Used for factory test modes 8 VDDIO O I/O voltage reference 9 INTB O Interrupt to host (push-pull) 10 SCL I I2C clock 11 SDA I/O I2C data 12 GND Ground 13 VBUS_IN I VBUS connected to USB receptacle 14 DM_CON I/O USB DM connected to USB receptacle 15 DP_CON I/O USB DP connected to USB receptacle 16 ID_CON I/O USB ID connected to USB receptacle Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback 3 Product Folder Link(s): TSU6111A |
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