AS1160 datasheet(3/29 Pages) AMSCO

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AS1160/AS1161

Datasheet - P i n o u t

4 Pinout

Pin Assignments and Descriptions

Figure 2. AS1160 Pin Assignments (Top View)

Table 1. AS1160 Pin Descriptions

Pin Number

Pin Name

Description

See Figure 2

DIN0:DIN9

Data Input. LVTTL levels inputs. Data on these pins are loaded into a 10-bit input

TCKR/FN

Transmit Clock Rising/Falling Strobe Select. LVTTL level input. Selects TCLK

active edge for strobing of DINx data.

1 = Rising edge.

0 = Falling edge.

DO+

+ Serial Data Output. Non-inverting Bus LVDS differential output.

DO-

- Serial Data Output. Inverting Bus LVDS differential output.

DEN

Serial Data Output Enable. LVTTL level input. If DEN is set to logic low the Bus LVDS

outputs are in tri-state condition.

PWDNN

Powerdown. LVTTL level input. Driving this pin low shuts down the PLL, tri-states the

outputs and puts the device into low power sleep mode.

TCLK

Transmit Clock. LVTTL level input. Input for 20MHz to 66MHz system clock.

SYNC1,

SYNC2

Synchronization. LVTTL level input. Assertion of SYNC (high) for at least 5 clock

cycles to be transmit a synchronization signal (SYNCPAT) on the Bus LVDS serial

output. Synchronization symbols continue to be sent if SYNCx continues to be

asserted. SYNC1 and SYNC2 pins are combined through an OR gate.

DVDD

+3.0V to +3.6V Digital Circuit Power Supply. This is the supply for all digital circuitry.

DGND

Digital Circuit Ground. GND reference point for the digital part of the AS1160.

AVDD

+3.0V to +3.6V Analog Power Supply (PLL and Analog Circuits). AVDD and DVDD

should be at the same potential and must not be more than 0.3V apart even on

transient basis. Both supplys should be decoupled by a capacitor of typically 10nF.

AGND

Analog Ground (PLL and Analog Circuits).

TDI

IEEE 1149.1 Test Data Input

TDO

IEEE 1149.1 Test Data Output

TMS

IEEE 1149.1 Test Mode Select Input

TCK

IEEE 1149.1 Test Clock Input

TRSTN

IEEE 1149.1 Test Reset Input

N/C

No Connection. Leave open-circuit, do not connect these pins.

DGND

N/C

DIN0

SYNC1

AVDD

N/C

DIN1

N/C

SYNC2

AVDD

AGND

AVDD

DIN3

DGND

DVDD

N/C

AGND

PWDNN

DIN5

DIN2

DIN4

N/C

DO-

DEN

DO+

DIN7

DIN6

TMS

TCLK

DVDD

DGND

AGND

TDI

DIN8

TCK

DIN9

DGND

N/C

AGND

TDO

TRSTN

TCKR/FN

DGND

AVDD

N/C

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