LTC4253 datasheet(23/36 Pages) LINER

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LTC4252-1/LTC4252-2

LTC4252A-1/LTC4252A-2

425212fd

APPLICATIONS INFORMATION

satisfied before a GATE start-up cycle begins. SS ramps up

as dictated by RSS • CSS; GATE is held low by the analog

current limit amplifier until SS crosses 20 • VOS. Upon

releasing GATE, 58μA sources into the external MOSFET

gate and compensation network. When the GATE voltage

reaches the MOSFET’s threshold, current begins flowing

into the load capacitor at time point 5. At time point 6,

load current reaches the SS control level and the analog

current limit loop activates. Between time points 6 and 8,

the GATE voltage is servoed, the SENSE voltage is regulated

at VACL(t) and soft-start limits the slew rate of the load

current. If the SENSE voltage (VSENSE – VEE) reaches the

VCB threshold at time point 7, the circuit breaker TIMER

activates. The TIMER capacitor, CT, is charged by a (230μA

+ 8 • IDRN) current pull-up. As the load capacitor nears full

charge, load current begins to decline. At point 8, the load

current falls and the SENSE voltage drops below VACL(t).

The analog current limit loop shuts off and the GATE pin

ramps further. At time point 9, the SENSE voltage drops

below VCB and the fault TIMER cycle ends, followed by a

5.8μA discharge cycle (cool off). When GATE ramps past

VGATEH threshold at time point 10, PWRGD pulls low. At

time point 11, GATE reaches its maximum voltage as

determined by VIN.

5.8μA

58μA

5.8μA

58μA

GATE

START-UP

INITIAL TIMING

UV CLEARS VUVHI, CHECK OV < VOVHI, GATE < VGATEL, SENSE < VCB

OS AND TIMER < VTMRL

3 4 56

8 9

TIMER CLEARS VTMRL, CHECK GATE < VGATEL, SENSE < VCB

1011

425212 F10

GND – VEE OR

(–48RTN) – (–48V)

UV/OV

VIN

TIMER

GATE

SENSE

VOUT

DRAIN

PWRGD

VLKO

VUVHI

VACL

VCB

DRN

VIN – VGATEH

VDRNL

VDRNCL

CB + VOS)

ACL + VOS)

VGATEL

VTMRL

VTMRH

Figure 10. Power-Up Timing with a Short Pin (All Waveforms Are Referenced to VEE)

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