EDJ2104BASE datasheet(21/148 Pages) ELPIDA

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EDJ2104BASE, EDJ2108BASE

Preliminary Data Sheet E1505E20 (Ver. 2.0)

[Differential Output Slew Rate Definition]

Measured

Description

From

Defined by

Differential output slew rate for

rising edge

VOLdiff (AC)

VOHdiff (AC)

VOHdiff(AC) – VOLdiff (AC)

∆TRdiff

Differential output slew rate for

falling edge

VOHdiff (AC)

VOLdiff (AC)

VOHdiff (AC) – VOLdiff (AC)

∆TFdiff

∆TRdiff

∆TFdiff

VOHdiff (AC)

− VOLdiff (AC)

∆TFdiff

Falling slew =

VOHdiff (AC)

VOLdiff (AC)

VOHdiff (AC)

− VOLdiff (AC)

∆TRdiff

Rising slew =

Differential Input Slew Rate Definition for DQS, /DQS and CK, /CK

Output Slew Rate (RON = RZQ/7 setting)

Parameter

Symbol

Speed

min.

max.

Unit

Notes

Output slew rate

(Single-ended)

SRQse

DDR3-800

DDR3-1066

DDR3-1333

DDR3-1600

2.5

V/ns

Output slew rate

(Differential)

SRQdiff

DDR3-800

DDR3-1066

DDR3-1333

DDR3-1600

V/ns

Remark: SR = slew rate. se = single-ended signals. diff = differential signals. Q = Query output

Note: 1.In two cases, a maximum slew rate of 6V/ns applies for a single DQ signal within a byte lane.

(a) is defined for a single DQ signal within a byte lane which is switching into a certain direction (either from

high to low or low to high) while all remaining DQ signals in the same byte lane are static (i.e. they stay at

either high or low).

(b) is defined for a single DQ signal within a byte lane which is switching into a certain direction (either from

high to low or low to high) while all remaining DQ signals in the same byte lane are switching into the

opposite direction (i.e. from low to high or high to low respectively). For the remaining DQ signal switching

into the opposite direction, the regular maximum limit of 5V/ns applies.

Reference Load for AC Timing and Output Slew Rate

RT =25

Ω

VDDQ

CK, /CK

VTT = VSSQ/2

DUT

DQS,

/DQS

Reference Output Load

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