MPC8378E_12 datasheet(56/128 Pages) FREESCALE

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MPC8378E PowerQUICC II Pro Processor Hardware Specifications, Rev. 8

Freescale Semiconductor

This means that data delay should be equal or less than the clock delay in the ideal case where

tSHSCLKL =10 ns:

tDATA_DELAY – tCLK_DELAY < 10 – 6 – 4

tDATA_DELAY – tCLK_DELAY < 0

11.3.1.2

High-Speed Write Meeting Hold (Minimum Delay)

The following equations show how to calculate the allowed skew range between the SD_CLK and

SD_DAT/CMD signals on the PCB.

tCLK_DELAY < tSHSCKL + tSHSKHOX + tDATA_DELAY – tIH

Eqn. 13

tCLK_DELAY – tDATA_DELAY < tSHSCKL + tSHSKHOX – tIH

Eqn. 14

This means that clock can be delayed versus data up to 8 ns (external delay line) in ideal case of

tSHSCLKL =10 ns:

tCLK_DELAY – tDATA_DELAY < 10 + 0 – 2

tCLK_DELAY – tDATA_DELAY < 8

11.3.2

High-Speed Input Path (Read)

This figure provides the data and command input timing diagram.

Figure 35. High-Speed Input Path

For the input path, the device eSDHC expects to sample the data 1.5 internal clock cycles after it was

driven by the SD card. Since in this mode the SD card drives the data at the rising edge of the clock, a

sufficient delay to the clock and the data must exist to ensure it will not be sampled at the wrong internal

tCLK_DELAY

Output from the

SD CLK at

the Card Pin

SD Card Pins

tSHSIVKH

Driving

Edge

Sampling

Edge

tOH

tDATA_DELAY

tODLY

tSHSCK (Clock Cycle)

1/2 Cycle

tSHSIXKH

Right Edge

Wrong Edge

(MPC8378E Input Hold)

(MPC8378E Input Setup)

Input at the

MPC8378E Pins

SD CLK at the

MPC8378E Pin

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