MPL3115A2

Sensors

Freescale Semiconductor, Inc.

7

3.1

1.

All values referred to VIH(min) and VIL(max) levels.

Ref

Symbol

Parameter

Unit

Condition

Min

Max

SCL Clock Frequency

Pull-up = 1 k

 C

0

400

KHz

SCL Clock Frequency

Pull-up = 1 k

 C

0

4

MHz

Bus free time between STOP and START condition

1.3

µs

Repeated START Hold Time

0.6

µs

Repeated START Setup Time

0.6

µs

0.6

µs

2.

3.

The device must internally provide a hold time of at least 300 ns for the SDA signal (with respect to the VIH(min) of the SCL signal) to bridge

the undefined region of the falling edge of SCL.

(4)

4.

ns

SDA Setup Time

5.

automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of

ns

SCL Clock Low Time

1.3

µs

10

SCL Clock High Time

0.6

µs

11

SDA and SCL Rise Time

(6)

6.

300

ns

12

7.

250 ns. This allows series protection resistors to be connected in between the SDA and the SCL pins and the SDA/SCL bus lines without

8.

In Fast Mode Plus, fall time is specified the same for both output stage and bus timing. If series resistors are used, designers should allow

for this when considering bus timing.

(6)

300

ns

13

Pulse width of spikes that are suppressed by internal

input filter

50

ns