HS7541A

12-Bit CMOS Multiplying DAC

© Copyright 2000 Sipex Corporation

3

SPECIFICATIONS (continued)

(T

PARAMETER

MIN.

TYP.

MAX.

UNIT

CONDITIONS

DIGITAL INPUTS

Logic Levels

V

IH

2.4

V

DD

Volts

2.4

Volts

Note 5

V

IL

-0.3

0.8

Volts

0.8

Volts

Note 5

Input Current

±1.0

µAV

±10

µA

Note 5 and 15

Input Capacitance

V

Bits 1—12

8

pF

Note 5

Coding

Unipolar

Binary

Bipolar

Offset Binary

POWER REQUIREMENTS

Voltage Range

+5

+15

Volts

Note 16

+16

Volts

Note 5

Supply Current

2.0

2.5

mA

All digital inputs V

2.5

mA

Note 5; all digital inputs V

V

IH

0.2

0.5

mA

All digital inputs 0V or 5V to

V

DD

1.0

mA

Note 5; all digital inputs 0V or

5V to V

DD

ENVIRONMENTAL AND MECHANICAL

Operating Temperature

-AK, -AJ

0

+70

°C

-AB, -AA

-40

+85

°C

Storage Temperature

-65

+150

°C

Package

-AK, -AJ

18-pin plastic DIP, 20-pin PLCC, 18–pin SOIC

Notes and Cautions:

1.

Do not apply voltages higher than VDD or less than GND potential on any terminal other than V

2.

The digital inputs are diode-clamp protected against ESD damage. However, permanent damage may occur

on unprotected units from high-energy electrostatic fields. Keep units in conductive foam at all times until

ready to use.

3.

Use proper anti-static handling procedures.

4.

Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the

device. This is a stress rating only and functional operation at or above these specifications is not implied.

Exposure to the above maximum rated conditions for extended periods may affect device reliability.

5.

From T

6.

Integral Non-linearity is measured as the arithmetic mean value of the magnitudes of the greatest positive

deviation and the greatest negative deviation from the theoretical value of any given input combination.

7.

Differential Non-linearity is the deviation of an output step from the theoretical value of 1 LSB for any two

adjacent digital input codes.

8.

AC performance characteristics are included for design guidance only and are subject to sample testing only.

9.

R

analog output.

10.

Settling to

±0.01% FSR (strobed); all data inputs 0V to V

11.

V

12.

V

13.

V

14.

Guaranteed by design, but not production tested.

15.

Logic inputs are MOS gates. I

16.

Accuracy is guaranteed at V

17.

Measured using internal feedback resistor with DAC loaded with all 1’s.

18.

All digital inputs = 0V.