SP9601DS/02

SP9601 12-Bit, Low-Power Voltage Output

© Copyright 2000 Sipex Corporation

3

SPECIFICATIONS (continued)

(Typical at 25˚C; T

PARAMETER

MIN.

TYP.

MAX.

UNITS

CONDITIONS

POWER REQUIREMENTS

Note 5

V

DD

+5V,

±3%; Note 4, 5

-J, -K

0.2

0.3

mA

-A, -B

0.2

0.45

mA

V

SS

-5V,

±3%; Note 4, 5

-J, -K

0.2

0.3

mA

-A, -B

0.2

0.45

mA

Power Dissipation

2

mW

SWITCHING

CHARACTERISTICS

CS Setup Time

(t

ns

SCLK Fall to CS

Fall Hold Time

(t

ns

SCLK Fall to CS Rise

Hold Time

(t

ns

SCLK High Width

(t

ns

SCLK Low Width

(t

ns

DIN Setup Time

(t

ns

DIN Hold Time

(t

ns

CS High Pulse Width

(t

ns

ENVIRONMENTAL AND

MECHANICAL

Operating Temperature

-J, -K

0

+70

°C

-A, -B

-40

+85

°C

Storage

-60

+150

°C

Package

–_N

8-pin Plastic DIP

–_S

8-pin 0.15" SOIC

Notes:

1.

Integral Linearity, for the SP9601, is measured as the arithmetic mean value of the magnitudes of

the greatest positive deviation and the greatest negative deviation from the theoretical value for any

given input condition.

2.

Differential Linearity is the deviation of an output step from the theoretical value of 1 LSB for any two

adjacent digital input codes.

3.

1 LSB = 2*V

4.

V

5.