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SL4013BN Scheda tecnica(PDF) 4 Page - System Logic Semiconductor

Il numero della parte SL4013BN
Spiegazioni elettronici  Dual D Flip-Flop
PDF  5 Pages
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Produttore elettronici  SLS [System Logic Semiconductor]
Homepage  http://www.slsemicon.co.kr/e_index.htm
Logo SLS - System Logic Semiconductor

SL4013BN Scheda tecnica(HTML) 4 Page - System Logic Semiconductor

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SL4013B
System Logic
Semiconductor
SLS
AC ELECTRICAL CHARACTERISTICS(C
L=50pF, RL=200 k
Ω, Input t
r=tf=20 ns)
VCC
Guaranteed Limit
Symbol
Parameter
V
≥-55°C
25
°C
≤125°C
Unit
fmax
Maximum Clock Frequency (Figure 1)
5.0
10
15
3.5
8
12
3.5
8
12
1.75
4
6
MHz
tPLH, tPHL
Maximum Propagation Delay, Clock to Q or Q
(Figure 1)
5.0
10
15
300
130
90
300
130
90
600
260
180
ns
tPLH
Maximum Propagation Delay, Set to Q or Reset
to Q (Figure 2)
5.0
10
15
300
130
90
300
130
90
600
260
180
ns
tPHL
Maximum Propagation Delay, Set to Q or Reset
to Q (Figure 2)
5.0
10
15
400
170
120
400
170
120
800
340
240
ns
tTLH, tTHL
Maximum Output Transition Time, Any Output
(Figure 1)
5.0
10
15
200
100
80
200
100
80
400
200
160
ns
CIN
Maximum Input Capacitance
-
7.5
pF
TIMING REQUIREMENTS(C
L=50pF, RL=200 k
Ω, Input t
r=tf=20 ns)
VCC
Guaranteed Limit
Symbol
Parameter
V
≥-55°C
25
°C
≤125°C
Unit
tw
Minimum Pulse Width, Clock (Figure 1)
5.0
10
15
140
60
40
140
60
40
280
120
80
ns
tw
Minimum Pulse Width, Set or Reset (Figure 2)
5.0
10
15
180
80
50
180
80
50
360
160
100
ns
tsu
Minimum Setup Time, Data to Clock
(Figure 3)
5.0
10
15
40
20
15
40
20
15
80
40
30
ns
th
Minimum Hold Time, Clock to Data
(Figure 3)
5.0
10
15
5
5
5
5
5
5
10
10
10
ns
tr, tf
Maximum Input Rise or Fall Time, Clock (Figure
1)
5.0
10
15
500
30
6
500
30
6
1000
60
12
µs



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