SL7101

System Logic

Semiconductor

SLS

Typical Application

Description of elements of application diagram

1. The resistance of R1 resistor is chosen in such a way so that to limit IC’s consumption

current (not more than 8 mA), and here the voltage drop is around 21-28V.

2. R2 resistor provides the necessary bias of the differential cascade.

3. R3 resistor is a loading one per input.

4. R4 resistor limits the charging current of C4 electrolytic capacitor are required to maintain

IC performance until the fuse is completely burn out. Its value is chosen correspondingly.

5. C1 electrolytic capacitor is a filtering one as per supply (around 1 – 10

µF ).

6. Ñ2 and C3 capacitors are filtering ones (not more than 1

µF)