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DAC712PLG4 Scheda tecnica(PDF) 9 Page - Texas Instruments |
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DAC712PLG4 Scheda tecnica(HTML) 9 Page - Texas Instruments |
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9 / 23 page  TIMING CHARACTERISTICS WR A ,A 0 1 D0-D15 t DH t AW t WP t DW t AH TIMING REQUIREMENTS A 0 , A1 Valid to End of WR A 0 , A1 Hold after End of WR DAC712 www.ti.com ................................................................................................................................................. SBAS023A – SEPTEMBER 2000 – REVISED JULY 2009 Figure 1. Timing Diagram At TA = –40°C to +85°C, +VCC = +12V or +15V, and –VCC = –12V or –15V, unless otherwise noted. DAC712 PARAMETER TEST CONDITIONS MIN TYP MAX UNIT tDW Data Valid to End of WR 50 ns tAW 50 ns tAH 10 ns tDH Data Hold after End of WR 10 ns tWP (1) Write Pulse Width 50 ns tCP CLEAR Pulse Width 200 ns (1) For single-buffered operation, tWP is 80ns minimum; see the Single-Buffered Operation section. Copyright © 2000–2009, Texas Instruments Incorporated Submit Documentation Feedback 9 Product Folder Link(s): DAC712 |
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