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Motore di ricerca datesheet componenti elettronici |
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Motore di ricerca datesheet componenti elettronici |
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SL74HC373N Scheda tecnica(PDF) 1 Page - System Logic Semiconductor |
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SL74HC373N Scheda tecnica(HTML) 1 Page - System Logic Semiconductor |
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1 / 5 page  SL74HC373 System Logic Semiconductor SLS Octal 3-State Noninverting Transparent Latch High-Performance Silicon-Gate CMOS The SL74HC373 is identical in pinout to the LS/ALS373. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LS/ALSTTL outputs. These latches appear transparent to data (i.e., the outputs change asynchronously) when Latch Enable is high. When Latch Enable goes low, data meeting the setup and hold time becomes latched. The Output Enable input does not affect the state of the latches, but when Output Enable is high, all device outputs are forced to the high-impedance state. Thus, data may be latched even when the outputs are not enabled. • Outputs Directly Interface to CMOS, NMOS, and TTL • Operating Voltage Range: 2.0 to 6.0 V • Low Input Current: 1.0 µA • High Noise Immunity Characteristic of CMOS Devices ORDERING INFORMATION SL74HC373N Plastic SL74HC373D SOIC TA = -55 ° to 125° C for all packages LOGIC DIAGRAM PIN 20=VCC PIN 10 = GND PIN ASSIGNMENT FUNCTION TABLE Inputs Output Output Enable Latch Enable D Q L H H H L H L L L L X No Change H X X Z X = Don’t Care Z = High Impedance |
Codice articolo simile - SL74HC373N |
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Descrizione simile - SL74HC373N |
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