6

Digital Phase Shifter

6-Bit, 1.4 - 2.4 GHz

Rev. V4

MAPS-010163

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typical. Mechanical outline has been fixed. Engineering samples and/or test data may be available.

Commitment to produce in volume is not guaranteed.

P/S

LE

Mode

1

X

Serial

0

N/A

Direct Parallel

Serial Mode

Direct Parallel Mode

The serial control interface (SERIN, CLK, LE,

SEROUT) is compatible with the SPI protocol. SPI

mode is activated when P/S is kept high. The 6-bit

serial word must be loaded with the MSB first. After

shifting in the 6 bit word, a rising edge on LE will set

the phase shifter to the desired state. While LE is

high the CLK is masked to protect the data while

implementing the change. SEROUT is SERIN

delayed by 6 clock cycles.

When P/S is low, the serial control interface is

disabled. When P/S is set high, Pins 22, 23, and 24

have the LE, CLK, and SER IN function.

In serial mode operation, the outputs will stay

constant while LE is kept low.

The parallel mode is enabled when P/S is set low. In

the direct parallel mode, the phase shifter is

controlled by the parallel control inputs directly.

When P/S is set low, Pins 22, 23, and 24 have the

D3, D2, and D1 function.

Modes of Operation:

Serial and Direct Parallel

Mode Truth Table

Serial Interface Timing Characteristics

Symbol

Parameter

Typical Performance

Units

-40°C

+25°C

+85°C

Min. Serial Clock Period

100

100

100

ns

Min. Control Set-up Time

20

20

20

ns

Min. Control Hold Time

20

20

20

ns

Min. LE Set-up Time

10

10

10

ns

Min. LE Pulse Width

10

10

10

ns

Min. Serial Clock Hold Time from LE

10

10

10

ns

Min. LE Pulse Spacing

630

630

630

ns

7. 0 = CMOS Low; 1 = CMOS High, X is CMOS Low or High

D5

D4

D3

D2

D1

Phase Shift

0

0

0

0

0

Reference Phase

0

0

0

0

1

5.6 deg

0

0

0

1

0

11.2 deg

0

0

1

0

0

22.5 deg

0

1

0

0

0

45 deg

1

0

0

0

0

90 deg

1

1

1

1

1

354.4 deg

D6

0

0

0

0

0

0

1

1

0

0

0

0

0

180 deg