TNETX3110 datasheet(54/65 Pages) TI1

Il numero della parte	TNETX3110

Spiegazioni elettronici	ThunderSWITCHE 8/3 ETHERNETE SWITCH WITH EIGHT 10-MBIT/S PORTS AND THREE 10-/100-MBIT/S PORTS

PDF	65 Pages

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Produttore elettronici	TI1 [Texas Instruments]

Homepage	http://www.ti.com

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TNETX3110

ThunderSWITCH

™ 8/3 ETHERNET™ SWITCH

WITH 8 10-MBIT/S PORTS AND 3 10-/100-MBIT/S PORTS

SPWS047A – MARCH 1998 – REVISED APRIL 1999

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

10-/100-Mbit/s transmit ports (08, 09, and 10)

timing requirements (see Figure 14)†

NO.

MIN

MAX

UNIT

tc(MxxTCLK)

Cycle time, MxxTCLK

tw(MxxTCLKL)

Pulse duration, MxxTCLK low

tw(MxxTCLKH)

Pulse duration, MxxTCLK high

† xx = ports 08, 09, and 10

operating characteristics over recommended operating conditions (see Note 8 and Figure 14)†

NO.

PARAMETER

MIN

MAX

UNIT

td(MxxTXD)

Delay time, from MxxTCLK

↑ to MxxTXD3–MxxTXD0 valid

td(MxxTXEN)

Delay time, from MxxTCLK

↑ to MxxTXEN valid

td(MxxTXER)

Delay time, from MxxTCLK

↑ to MxxTXER valid

† xx = ports 08, 09, and 10

NOTE 8: Both MxxCRS and MxxCOL are driven asynchronously by the PHY. MxxTXD3–MxxTXD0 is driven by the reconciliation sublayer

synchronous to the MxxTCLK. MxxTXEN is asserted and deasserted by the reconciliation sublayer synchronous to the MxxTCLK rising

edge. MxxTXER is driven synchronous to the rising edge of MxxTCLK.

MxxTXD3–MxxTXD0

MxxTXEN

MxxTXER

(outputs)

MxxTCLK

(input)

Figure 14. 10-/100-Mbit/s Transmit Ports

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