C =10pF

1

C =10pF

2

OPA

VSP5010

V

CLAMP

C

IN

CCDIN

SHD

V

CLAMP

SHP

CCD

Output

SHP

INPUTCLP

INPUT CLAMP (DUMMY PIXEL CLAMP)

HIGH PRECISION A/D CAPACITOR

VSP5010

The CDS circuit can be configured as a sample-and-hold (S/H) circuit by the CDS/SH SEL pin. A simplified S/H

circuit block diagram is shown in Figure 6.

In CDS mode, the signal voltage is received as the voltage difference between the sampled voltage of SHP

input in S/H mode.

Figure 6. Simplified Sample-and-Hold (S/H) Circuit

Output from the CCD image sensor is ac-coupled with the VSP5010 through a capacitor. The purpose of the

input clamp is to reproduce the dc bias lost by ac coupling, and to supply an optimum dc bias for proper device

operation at the CDS/SH circuit. Refer to Figure 5 and Figure 6 for simplified block diagrams of the input clamp

circuit.

The input signal level is clamped to the internal reference voltage by activating both SHP (during CDS mode;

activate SHD during SH mode) and INPUTCLP during the CCD dummy pixel output period.

The ADC block of the VSP5010 consists of a pipeline architecture. This converter has a complete differential

circuit configuration and error correction circuit, and ensures 14-bit resolution.

Circuits that generate the necessary reference voltage at the ADC are built inside the device, and are shown as

REFP (high-potential reference), REFN (low-potential reference), and CM (common-mode voltage) pins outside

the device. In order to assure ADC accuracy, these reference voltage pins must be sufficiently decoupled by a

capacitor (0.1

µF recommended).

Copyright © 2008, Texas Instruments Incorporated

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