ThunderLAN

™ TNETE100A

PCI ETHERNET

™ CONTROLLER

SINGLE-CHIP 10 BASE-T WITH MII FOR 100 BASE-T/100VG-AnyLAN

SPWS021B – OCTOBER 1995 – REVISED NOVEMBER 1996

16

POST OFFICE BOX 1443

test measurement

The test-load circuit shown in Figure 3 represents the programmable load of the tester pin electronics that are

used to verify timing parameters of the TNETE100A output signals.

(c) FIREF TEST CIRCUIT

(b) AXMTP AND AXMTN TEST LOAD (AC TESTING)

X1 – Fil – Mag 23Z90 (1:1)

(a) TTL OUTPUT TEST LOAD

180

Ω

FIREF

AXMTN

AXMTP

78

Ω

Point

Test

CL

IOH

VLOAD

IOL

Point

Test

Test

Under

Output

TTL

50

Ω

FXMTN

FXMTP

X1

50

Ω

50

Ω

Point

Test

50

Ω

X2

50

Ω

50

Ω

25

Ω

25

Ω

FXMTN

FXMTP

Point

Test

50

Ω

50

Ω

50

Ω

50

Ω

Point

Test

(e) FXMTP AND FXMTN TEST LOAD (DC TESTING)

(d) FXMTP AND FXMTN TEST LOAD (AC TESTING)

X2 – Fil – Mag 23Z128 (1:

√2)

Where: IOL

= Refer to IOL in recommended operating conditions

IOH

= Refer to IOH in recommended operating conditions

VLOAD

= 1.5 V, typical dc-level verification or

0.7 V, typical timing verification

CL

= 18 pF, typical load-circuit capacitance

Figure 3. Test and Load Circuit