ST7570

Physical layer

Doc ID 17526 Rev 2

21/26

9.2

Bit timing

The data communication is synchronized to the mains zero-crossing through an internal

PLL. The bit time is dynamically adapted in order to have always 24 or 48 bits in each mains

cycle, according to the desired configuration (Figure 13). The resulting bit-rate is thus

dependent on the instantaneous mains frequency. With a nominal frequency of 50 Hz, the

resulting bit-rate is 1200 bps in the case of 24 bit/mains cycle, while 2400 bps in the case of

48 bit/mains cycle.

Figure 13.

Bit timing