S29JL032J datasheet(3/63 Pages) SPANSION

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Publication Number S29JL032J_00

Revision 06

Issue Date December 16, 2011

Distinctive Characteristics

Architectural Advantages

 Simultaneous Read/Write operations

– Data can be continuously read from one bank while executing

erase/program functions in another bank.

– Zero latency between read and write operations

 Multiple bank architecture

– Four bank architectures available (refer to Table 8.2 on page 17).

 Boot sectors

– Top or bottom boot sector configurations available

– Any combination of sectors can be erased

 Manufactured on 0.11 µm Process Technology

 Secured Silicon Region: Extra 256 byte sector

– Factory locked and identifiable: 16 bytes available for secure,

random factory Electronic Serial Number; verifiable as factory

locked through autoselect function

– Customer lockable: One-time programmable only. Once locked,

data cannot be changed

 Zero power operation

– Sophisticated power management circuits reduce power consumed

during inactive periods to nearly zero.

 Compatible with JEDEC standards

– Pinout and software compatible with single-power-supply flash

standard

Package Options

 48-ball Fine-pitch BGA

 48-pin TSOP

Performance Characteristics

 High performance

– Access time as fast as 60 ns

– Program time: 6 µs/word typical using accelerated programming

function

 Ultra low power consumption (typical values)

– 2 mA active read current at 1 MHz

– 10 mA active read current at 5 MHz

– 200 nA in standby or automatic sleep mode

 Cycling endurance: 1 million cycles per sector typical

 Data retention: 20 years typical

Software Features

 Supports Common Flash Memory Interface (CFI)

 Erase suspend/Erase resume

– Suspends erase operations to read data from, or program data to, a

sector that is not being erased, then resumes the erase operation.

 Data# polling and toggle bits

– Provides a software method of detecting the status of program or

erase operations

 Unlock bypass program command

– Reduces overall programming time when issuing multiple program

command sequences

Hardware Features

 Ready/Busy# output (RY/BY#)

– Hardware method for detecting program or erase cycle completion

 Hardware reset pin (RESET#)

– Hardware method of resetting the internal state machine to the read

mode

 WP#/ACC input pin

– Write protect (WP#) function protects the two outermost boot

sectors regardless of sector protect status

– Acceleration (ACC) function accelerates program timing

 Sector protection

– Hardware method to prevent any program or erase operation within

a sector

– Temporary Sector Unprotect allows changing data in protected

sectors in-system

General Description

The S29JL032J is a 32 Mbit, 3.0 volt-only flash memory device, organized as 2,097,152 words of 16 bits each or 4,194,304

bytes of 8 bits each. Word mode data appears on DQ15–DQ0; byte mode data appears on DQ7–DQ0. The device is designed

to be programmed in-system with the standard 3.0 volt VCC supply, and can also be programmed in standard EPROM

programmers. The device is available with an access time of 60, or 70 ns and is offered in a 48-ball FBGA or a 48-pin TSOP

package. Standard control pins—chip enable (CE#), write enable (WE#), and output enable (OE#)—control normal read and

write operations, and avoid bus contention issues. The device requires only a single 3.0 volt power supply for both read and

write functions. Internally generated and regulated voltages are provided for the program and erase operations.

S29JL032J

32 Megabit (4M x 8-Bit/2M x 16-Bit)

CMOS 3.0 Volt-Only, Simultaneous Read/Write

Flash Memory

Data Sheet

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