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SMB117 Scheda tecnica(PDF) 13 Page - Summit Microelectronics, Inc.

Il numero della parte SMB117
Spiegazioni elettronici  High-power, Four-channel Programmable DC-DC System Power Managers
PDF  32 Pages
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Produttore elettronici  SUMMIT [Summit Microelectronics, Inc.]
Homepage  http://www.summitmicro.com
Logo SUMMIT - Summit Microelectronics, Inc.

SMB117 Scheda tecnica(HTML) 13 Page - Summit Microelectronics, Inc.

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SMB113A/B/SMB117/A
Preliminary Information
Summit Microelectronics, Inc
2111 2.6 9/16/2010
13
Note 6: Guaranteed by Design.
Figure 4 – I
2C timing diagram
I
2C-2 WIRE SERIAL INTERFACE AC OPERATING CHARACTERISTICS – 100 kHz
(Over recommended operating conditions, unless otherwise noted. All voltages are relative to GND.)
Symbol
Description
Conditions
100kHz
Min
Typ
Max
Units
fSCL
SCL clock frequency
0
100
kHz
TLOW
Clock low period
4.7
μs
THIGH
Clock high period
4.0
μs
tBUF
Bus free time
Before new transmission –
Note 6
4.7
μs
tSU:STA
Start condition setup time
4.7
μs
tHD:STA
Start condition hold time
4.0
μs
tSU:STO
Stop condition setup time
4.7
μs
tAA
Clock edge to data valid
SCL low to valid SDA
(cycle n)
0.2
3.5
μs
tDH
Data output hold time
SCL low (cycle n+1) to SDA
change
0.2
μs
tR
SCL and SDA rise time
Note 6
1000
ns
tF
SCL and SDA fall time
Note 6
300
ns
tSU:DAT
Data in setup time
250
ns
tHD:DAT
Data in hold time
0
ns
TI
Noise filter SCL and SDA
Noise suppression
136
ns
tWR_CONFIG
Write cycle time config
Configuration registers
10
ms
tWR_EE
Write cycle time EE
Memory array
5
ms
t
R
t
F
t
HIGH
t
LOW
t
SU:STA
t
HD:STA
t
SU:DAT
t
HD:DAT
t
SU:STO
t
BUF
t
DH
t
AA
SCL
SDA
(IN)
SDA
(OUT)
t
WR (For Write Operation Only)
TIMING DIAGRAMS



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