41594B datasheet(260/372 Pages) MICROCHIP

260 / 372 page

PIC12LF1840T48A

DS41594B-page 260

Preliminary

 2011-2012 Microchip Technology Inc.

: SSP1 CONTROL REGISTER 2

R/W-0/0

R-0/0

R/W-0/0

R/S/HS-0/0 R/S/HS-0/0

R/S/HS-0/0

R/W/HS-0/0

GCEN

ACKSTAT

ACKDT

ACKEN

RCEN

PEN

RSEN

SEN

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

u = Bit is unchanged

x = Bit is unknown

-n/n = Value at POR and BOR/Value at all other Resets

‘1’ = Bit is set

‘0’ = Bit is cleared

HC = Cleared by hardware

S = User set

bit 7

GCEN: General Call Enable bit (in I2C Slave mode only)

1 = Enable interrupt when a general call address (0x00 or 00h) is received in the SSP1SR

0 = General call address disabled

bit 6

ACKSTAT: Acknowledge Status bit (in I2C mode only)

1 = Acknowledge was not received

0 = Acknowledge was received

bit 5

ACKDT: Acknowledge Data bit (in I2C mode only)

In Receive mode:

Value transmitted when the user initiates an Acknowledge sequence at the end of a receive

1 = Not Acknowledge

0 = Acknowledge

bit 4

ACKEN: Acknowledge Sequence Enable bit (in I2C Master mode only)

In Master Receive mode:

1 = Initiate Acknowledge sequence on SDA and SCL pins, and transmit ACKDT data bit.

Automatically cleared by hardware.

0 = Acknowledge sequence Idle

bit 3

RCEN: Receive Enable bit (in I2C Master mode only)

1 = Enables Receive mode for I2C

0 = Receive Idle

bit 2

PEN: Stop Condition Enable bit (in I2C Master mode only)

SCK Release Control:

1 = Initiate Stop condition on SDA and SCL pins. Automatically cleared by hardware.

0 = Stop condition Idle

bit 1

RSEN: Repeated Start Condition Enabled bit (in I2C Master mode only)

1 = Initiate Repeated Start condition on SDA and SCL pins. Automatically cleared by hardware.

0 = Repeated Start condition Idle

bit 0

SEN: Start Condition Enabled bit (in I2C Master mode only)

In Master mode:

1 = Initiate Start condition on SDA and SCL pins. Automatically cleared by hardware.

0 = Start condition Idle

In Slave mode:

1 = Clock stretching is enabled for both slave transmit and slave receive (stretch enabled)

0 = Clock stretching is disabled

Note 1:

For bits ACKEN, RCEN, PEN, RSEN, SEN: If the I2C module is not in the Idle mode, this bit may not be

set (no spooling) and the SSP1BUF may not be written (or writes to the SSP1BUF are disabled).

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