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AD5124 Scheda tecnica(PDF) 13 Page - Analog Devices |
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AD5124 Scheda tecnica(HTML) 13 Page - Analog Devices |
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13 / 36 page  Data Sheet AD5124/AD5144/AD5144A Rev. A | Page 13 of 36 ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Table 7. Parameter Rating VDD to GND −0.3 V to +7.0 V VSS to GND +0.3 V to −7.0 V VDD to VSS 7 V VLOGIC to GND −0.3 V to VDD + 0.3 V or +7.0 V (whichever is less) VA, VW, VB to GND VSS − 0.3 V, VDD + 0.3 V IA, IW, IB Pulsed1 Frequency > 10 kHz RAW = 10 kΩ ±6 mA/d2 RAW = 100 kΩ ±1.5 mA/d2 Frequency ≤ 10 kHz RAW = 10 kΩ ±6 mA/√d2 RAW = 100 kΩ ±1.5 mA/√d2 Digital Inputs −0.3 V to VLOGIC + 0.3 V or +7 V (whichever is less) Operating Temperature Range, TA3 −40°C to +125°C Maximum Junction Temperature, TJ Maximum 150°C Storage Temperature Range −65°C to +150°C Reflow Soldering Peak Temperature 260°C Time at Peak Temperature 20 sec to 40 sec Package Power Dissipation (TJ max − TA)/θJA ESD4 4 kV FICDM 1.5 kV 1 Maximum terminal current is bounded by the maximum current handling of the switches, maximum power dissipation of the package, and maximum applied voltage across any two of the A, B, and W terminals at a given resistance. 2 d = pulse duty factor. 3 Includes programming of EEPROM memory. 4 Human body model (HBM) classification. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. THERMAL RESISTANCE θJA is defined by the JEDEC JESD51 standard, and the value is dependent on the test board and test environment. Table 8. Thermal Resistance Package Type θJA θJC Unit 24-Lead LFCSP 351 3 °C/W 20-Lead TSSOP 1431 45 °C/W 1 JEDEC 2S2P test board, still air (0 m/sec airflow). ESD CAUTION |
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