AD5310

–4–

REV. A

PIN CONFIGURATIONS

TOP VIEW

(Not to Scale)

6

5

4

1

2

3

GND

SYNC

SCLK

DIN

AD5310

SOT-23

TOP VIEW

(Not to Scale)

8

7

6

5

1

2

3

4

NC

AD5310

SYNC

GND

SCLK

DIN

NC

SOIC

NC = NO CONNECT

PIN FUNCTION DESCRIPTIONS

SOT-23 Pin Numbers

Pin

No.

Mnemonic

Function

Analog output voltage from DAC. The output amplifier has rail-to-rail operation.

2

GND

Ground reference point for all circuitry on the part.

coupled to GND.

4

DIN

Serial Data Input. This device has a 16-bit shift register. Data is clocked into the register on the

falling edge of the serial clock input.

5

SCLK

Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock

input. Data can be transferred at rates up to 30 MHz.

6

SYNC

Level triggered control input (active low). This is the frame synchronization signal for the input

data. When

SYNC goes low, it enables the input shift register and data is transferred in on the

falling edges of the following clocks. The DAC is updated following the 16th clock cycle unless

SYNC is taken high before this edge in which case the rising edge of SYNC acts as an interrupt and

the write sequence is ignored by the DAC.