AWC6325P9 datasheet(6/11 Pages) ANADIGICS

6 / 11 page

PRELIMINARY DATA SHEET - Rev 1.3

05/2012

AWC6325

APPLICATION INFORMATION

To ensure proper performance, refer to all related

Application Notes on the ANADIGICS web site:

http://www.anadigics.com

Shutdown Mode

The power amplifier may be placed in a shutdown

mode by applying logic low levels (see Operating

Ranges table) to the VENABLE and VMODE pads.

Table 6: Bias Control

Bias Modes

The power amplifier may be placed in Low, Medium,

or High Bias modes by applying the appropriate logic

level (see Operating Ranges table) to the VMODE pin.

The Bias Control table lists the recommended modes

of operation for various applications.

APPLICATION

POUT

LEVELS

BIAS

MODE

VEN_CELL

VEN_PCS

VMODE1

VMODE2

VCC

VBATT

Low Bias Mode

< +10 dBm

Low

+1.8 V

0.8 - 4.35 V

> 3.2 V

Medium Bias Mode

> +10 dBm

< +16 dBm

Medium

+1.8 V

0 V

0.8 - 4.35 V

> 3.2 V

High Bias Mode

> +16 dBm

High

+1.8 V

0 V

1.3 - 4.35 V

> 3.2 V

Shutdown

0 V

3.2 - 4.35 V

>3.2 V

Figure 3: Recommended ON/OFF Timing Sequence

Notes:

(1) Level might be changed after RF is ON.

(2) RF OFF defined as PIN ≤ -30 dBm.

(3) Switching simultaneously between VMODE and VEN is not recommended.

VEN_CELL,PCS

VCC, VCCA

note 1

RFIN_CELL,PCS

notes 1,2

OFF Sequence

Referenced After 90% of Rise

Time

Referenced Before10% of Fall

Time

ON Sequence

On Sequence Start

T_0N=0µ

T_0N+1µS

T_0N+3µS

Off Sequence Start

T_0FF= 0µ

T_0FF+2µST_0FF+3µS

Vcontrols

Venable/Vmode(s)

Rise/Fall Max 1

µS

Defined at 10% to 90%

of Min/Max Voltage

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