AD6623ABC datasheet(27/40 Pages) AD

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AD6623

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Sync bits are set low (External Address 5). All appropriate

control and memory registers (filter) are then loaded. The

Start Update Hold-Off Counter (0xn00) should be set to 0.

2. Set the appropriate program and sleep bits low (Ext Address 4).

This enables the channel. The channel must have Program

and Sleep Mode low to activate a channel.

NCO SHADOW

NCO

NCO PHASE

ACCUMULATOR

ENA

CLR

SET

SLEEP

HOP

HOLDOFF

HOP

SYNC

START

HOLDOFF

COUNTER

START

COUNTER

RESET PIN

CLK

START

SYNC

CLR

C = 1

C = 0

ENA

C = 1

C = 0

ENA

Figure 34. NCO Shadow Register and Hold-Off Counter

Start with Soft Sync

The AD6623 includes the ability to synchronize channels or chips

under microprocessor control. One action to synchronize is the

start of channels or chips. The Start Update Hold-Off Counter

(0xn00) in conjunction with the Start bit and Sync bit (Ext

Address 5) allow this synchronization. Basically the Start Update

Hold-Off Counter delays the Start of a channel(s) by its value

(number of AD6623 CLKs). The following method is used to syn-

chronize the start of multiple channels via microprocessor control.

1. Set the appropriate channels to sleep mode (a hard reset to the

AD6623 Reset pin brings all four channels up in sleep mode).

2. Write the Start Update Hold-Off Counter(s) (0xn00) to the

appropriate value (greater than 1 and less than 2

16–1). If the

chip(s) is not initialized, all other registers should be loaded

at this step.

3. Write the Start bit and the SyncX(s) bit high (Ext Address 5).

4. This starts the Start Update Hold-Off Counter counting down.

The counter is clocked with the AD6623 CLK signal. When it

reaches a count of one the sleep bit of the appropriate channel(s)

is set low to activate the channel(s).

Start with Pin Sync

A Sync pin is provided on the AD6623 to provide the most

accurate synchronization, especially between multiple AD6623s.

Synchronization of start with an external signal is accomplished

with the following method.

1. Set the appropriate channels to sleep mode (a hard reset to the

AD6623 Reset pin brings all four channels up in sleep mode).

2. Write the Start Update Hold-Off Counter(s) (0xn00) to the

appropriate value (greater than 1 and less than 2

16–1). If the

chip(s) is not initialized, all other registers should be loaded

at this step.

3. Set the Start on Pin Sync bit and the appropriate Sync Pin

Enable high (0xn01).

4. When the Sync pin is sampled high by the AD6623 CLK this

enables the count down of the Start Update Hold-Off Counter.

The counter is clocked with the AD6623 CLK signal. When it

reaches a count of one the sleep bit of the appropriate channel(s)

is set low to activate the channel(s).

Hop

A jump from one NCO frequency to a new NCO frequency. This

change in frequency can be synchronized via microprocessor

control or an external Sync signal as described below.

To set the NCO frequency without synchronization the following

method should be used.

Set Frequency No Hop

1. Set the NCO Frequency Hold-Off counter to 0.

2. Load the appropriate NCO frequency. The new frequency

will be immediately loaded to the NCO.

Hop with Soft Sync

The AD6623 includes the ability to synchronize a change in NCO

frequency of multiple channels or chips under microprocessor

control. The NCO Frequency Hold-Off counter (0xn03) in con-

junction with the Hop bit and the Sync bit (Ext Address 5) allow

this synchronization. Basically the NCO Frequency Hold-Off

counter delays the new frequency from being loaded into the NCO

by its value (number of AD6623 CLKs). The following method

is used to synchronize a hop in frequency of multiple channels

via microprocessor control.

1. Write the NCO Frequency Hold-Off (0xn03) counter to the

appropriate value (greater than 1 and less then 2

16–1).

2. Write the NCO Frequency register(s) to the new desired

frequency.

3. Write the hop bit and the Sync(s) bit high (Ext Address 5).

4. This starts the NCO Frequency Hold-Off counter counting

down. The counter is clocked with the AD6623 CLK signal.

When it reaches a count of one the new frequency is loaded

into the NCO.

Hop with Pin Sync

A Sync pin is provided on the AD6623 to provide the most

accurate synchronization, especially between multiple AD6623s.

Synchronization of hopping to a new NCO frequency with an

external signal is accomplished with the following method.

1. Write the NCO Frequency Hold-Off counter(s) (0xn03) to

the appropriate value (greater than 1 and less than 2

16–1).

2. Write the NCO Frequency register(s) to the new desired

frequency.

3. Set the Hop on Pin Sync bit and the appropriate Sync Pin

Enable high (0xn01).

4. When the Sync pin is sampled high by the AD6623 CLK

this enables the count down of the NCO Frequency Hold-Off

counter. The counter is clocked with the AD6623 CLK signal.

When it reaches a count of one the new frequency is loaded into

the NCO.

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