AD7724 datasheet(4/14 Pages) AD

4 / 14 page

REV. A

AD7724

–4–

TIMING CHARACTERISTICS

Limit at TMIN, TMAX

Parameter

(A Version)

Unit

Conditions/Comments

fMCLK

100

kHz min

Master Clock Frequency

MHz max

13 MHz for Specified Performance

ns min

Master Clock Period

0.45

× t

MCLK

ns min

Master Clock Input High Time

0.45

× t

MCLK

ns min

Master Clock Input Low Time

ns min

Data Hold Time After SCLK Rising Edge

ns min

RESET Pulsewidth

ns min

RESET Low Time Before MCLK Rising

× t

MCLK

ns max

DVAL High Delay After RESET Low

NOTE

Guaranteed by design.

OUTPUT

50pF

IOH

200 A

IOL

1.6mA

1.6V

Figure 2. Load Circuit for Access Time and Bus Relinquish Time

SCLK (O)

DATA (O)

NOTE:

O SIGNIFIES AN OUTPUT

Figure 3. Data Timing

MCLK (I)

RESET (I)

DVAL (O)

NOTE:

I SIGNIFIES AN INPUT

O SIGNIFIES AN OUTPUT

Figure 4. RESET Timing

(AVDD = 5 V

5%; DVDD = 5 V

5%; DVDD1 = 3 V

5%; AGND = DGND = 0 V, REF2A =

REF2B = 2.5 V, unless otherwise noted)

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