AD809

REV. A

–5–

USING THE AD809

Ground Planes

Use of one ground plane for connections to both analog and

digital grounds is recommended.

Power Supply Connections

Use of a 10

µF capacitor between V

mended. Care should be taken to isolate the +5 V power trace

vide the CLKOUT/CLKOUTN signals.

respectively) is recommended. Use of 0.1

µF capacitors between

IC power supply and ground is recommended. Power supply

decoupling should take place as close to the IC as possible.

Refer to the schematic, Figure 5, for advised connections.

Transmission Lines

Use of 50

Ω transmission lines are recommended for PECL

inputs.

Terminations

Termination resistors should be used for PECL input signals.

Metal, thick film, 1% tolerance resistors are recommended.

Termination resistors for the PECL input signals should be

placed as close as possible to the PECL input pins.

Connections from the power supply to load resistors for input

and output signals should be individual, not daisy chained. This

will avoid crosstalk on these signals.

A ceramic capacitor may be used for the loop damping capaci-

tor. A 22 nF capacitor provides a damping factor of 10.

Synthesizer Input

TTL/CMOSIN

Synthesizer Input

CLKIN/CLKINN

PECL INPUT

PLL Differential

Output Stage–

CLKOUT/CLKOUTN

80µA

OR

0µA

80µA

OR

0µA

500

Ω

DIFFERENTIAL

OUTPUT

2.6mA

460

Ω

460

Ω

500

Ω

7.5k

Ω

7.5k

Ω

500

Ω

40µA

40µA

Figure 4. Simplified Schematics

14

13

12

11

16

15

10

9

8

1

2

3

4

7

6

5

CLKOUTN

CLKOUT

CF1

CF2

MUX

CLKIN

CLKINN

TTL/CMOSIN

GND

J5

MUX

EXT

+5V

AD809

16-PIN SOIC

SOLDERED TO BOARD

C1

0.1µF

R6

3.65k

Ω

R5

301

Ω

R2

49.9

Ω

R1

49.9

Ω

JUMPER

W2

R16

301

Ω

GUARD RING

+5V

GND

C11

10µF

TP4

TP3

R7 100

Ω

R8 100

Ω

R12

154

Ω

R11

154

Ω

CD

TP1

TP2

C8

C7

C6

0.1µF

R4

100

Ω

R3

100

Ω

VECTOR PINS SPACED FOR THROUGH-HOLE

CAPACITOR ON VECTOR CUPS.

COMPONENT SHOWN FOR REFERENCE ONLY.

C5 0.1µF

J3

J4

C4 0.1µF

ECL INN

ECL IN

CLKOUTN

CLKOUT

J2

C3 0.1µF

J1

C2 0.1µF

50

Ω STRIP LINE

EQUAL LENGTH

JUMPER

W1

JUMPER

W3

R15

49.9

Ω

R14

49.9

Ω

J6

CLKIN

J7

CLKINN

C13 0.1µF

C14 0.1µF

J8

CMOS/TTL IN

C15 0.1µF

R13

49.9

Ω

C12

0.1µF

R17

3.65k

Ω

NOTE:

C7–C10 ARE 0.1µF BYPASS CAPACITORS

RIGHT ANGLE SMA CONNECTOR

OUTER SHELL TO GND PLANE

ALL RESISTORS ARE 1% 1/8 WATT SURFACE MOUNT

TPx

TEST POINTS ARE VECTOR PINS

C9

C10

PECLINN

PECLIN

Figure 5. Evaluation Board Schematic