eorex

EM488M1644VTF

Jan. 2011

www.eorex.com

Recommended Power On and Initialization

The following power on and initialization sequence guarantees the device is preconditioned to each user’s

specific needs. (Like a conventional DRAM) During power on, all V

and V

DD

simultaneously to the specified voltage when the input signals are held in the “NOP” state. The power on

voltage must not exceed V +0.3V on any of the input pins or V

DD

time)

After power on, an initial pause of 200 µs is required followed by a precharge of all banks using the

precharge command.

To prevent data contention on the DQ bus during power on, it is required that the DQM and CKE pins be

held high during the initial pause period. Once all banks have been precharged, the Mode Register Set

Command must be issued to initialize the Mode Register. A minimum of eight Auto Refresh cycles (CBR)

are also required, and these may be done before or after programming the Mode Register.

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