–6–

+

+

AD9066

CLKIN

OPTIONAL

BPF

OR LPF

PLL

CLOCK

1

6

11

28

27

26

25

24

23

20

19

18

17

16

15

A OUTPUTS

(INPHASE)

B OUTPUTS

(QUADRATURE)

0

90

RECEIVED SIGNAL

STRENGTH INDICATOR

AGC

DETECTOR

PTAT

VOLTAGE

10

VMID

10

100nF

330

100nF

4.7 F

330

BANDPASS

FILTER

AGC VOLTAGE

MIDPOINT

BIAS

GENERATOR

BIAS

CIRCUIT

–16dBM

LOCAL

OSCILLATOR

RF INPUT

(ANTENNA)

AD607

Figure 8. Digitizer with AD607 Receiver Circuit

Theory of Operation

The AD9066 dual ADC employs a patented interpolated flash

architecture. This architecture enables 64 possible quantization

levels with only 32 comparator preamplifiers. This keeps input

capacitance to a minimum. The midpoint of the reference lad-

der is fed back to the analog input, allowing easy biasing of the

ADC to midscale for ac coupled applications.

As shown in Figure 4d, a simple resistor is used to provide the

reference ladder midpoint to the analog input. The high imped-

ance MOS inputs of the comparators insure no static voltage

drop across the resistor. This eliminates the need for an active

buffer (and its inherent offsets) to set the reference midpoint at

the analog input.

The outputs of the comparators are converted to a 6-bit word

and converted to CMOS levels. The digital signals are latched at

six stages (two pipeline delays) in the signal path. The digital

outputs are CMOS with approximately equal rise and fall times.

The encode clock utilizes a CMOS input stage with TTL-

compatible (1.4 V) thresholds. Internal clock buffers minimize

external clock drive requirements.

REV. A

AD9066